Design And Implementation Of SerDes Chip Based On 8b/10b Architecture

With the increasing demand for high speed communication, the transmission interface technology related to high speed communication has become a hot research topic. Traditional parallel transmission interface technology development to today has been very difficult to have a greater potential to play, and serial interface which in many ways has advantages of gradually come into the field of vision, in this context, previously has not been fully played the potential of SerDes interface standard become more and more important technical standards.SerDes is Serializer(serial device) and Dserializer(deserializer) for short in English, which is a high-speed serial interface technology in mainstream. Two important features of it is the point to point and time division multiplexing. As a serial interface SerDes is also formed by the transmitter and the receiver, which two are integrated in one chip. As the 8B / 10 B SerDes has been widely used, the transmitter is formed by 8B / 10 B encoder, converter of parallel to serial, LVDS transmission circuit and the receiver mainly consists of a LVDS receiver circuit, clock and data recovery circuit, conventer of serial to parallel, 8B / 10 B decoder.This paper focuses on the key two modules on thedata channel in the SerDes chip, the 8b/10 b codec and LVDS transceiver circuit module. The codec circuit adopts the protocol IBM once proposed which has good DC balance. LVDS circuit is based on IEEE LVDS standard and designed according to the actual situation of the project. The encoding and decoding module and the LVDS transceiver module are combined in the simulation process. The scientific construction of the platform of verification on the mixed signal chip and constantly adjusted and optimized for the chip ensure that the two important modules on the chip data channel meet the requirements of the target.Moreover, this paper also studied ESD protection circuit which is relation to the SerDes chip reliability. This paper analysised the formation mechanism which ESD is based on, and then studied the ESD protection circuit structure. Finally it combined with the specific application to analysis the examples used in our project. After that, the layout design flow of the mixed signal circuit is summarized and implemented. Considered the point of view of the digital circuit and analog circuit this paper finally complete the planning, implementation and consolidation of the layout. At the end of this paper, the full chip were simulated under different conditions. In the premise of ensuring the correct logic function of the chip, performance indicators for the full chip we continue to adjust and optimize. In this process of appropriate simulation scheme we ensure the function and performance of the chip. In the design and implementation of the chip, the project has been continuously studied and modified to ensure the success of the chip.