Research On Verification And Testing Of SERDES Chip

Along with the progress of time and the development of science,today’s social demand for information has reached an unprecedented level. This is not only reflected in the hope that the amount of information is more abundant, but also on the rate of transmission of information put forward higher requirements. Ser Des technology is arises at the historic moment in this form, it has traditional parallel interface incomparable advantage in speed and has a smaller hardware overhead. Ser Des chip can be seen everywhere in today’s high-speed communication systems.In the process of integrated circuit design, verification and testing is an extremely important link, they often occupy most of the design time. With more and more complex integrated circuits, more and more challenges to verify and test. And SERDES chip as a complex high-speed integrated circuit chip, how to carry out effective verification and testing, is very worthy of research.First of all, the paper illustrates SerDes technology and Ser Des technology commonly used four kinds of architecture, including the parallel clock Ser Des, embedded clock SerDes, bit interleaved Ser Des and 8b/10 bSERDES, and emphatically introduced the study 8B / 10 B encoding architecture SerDes chip internal structure, which digital circuit part mainly coding and decoding circuit, analog circuit part mainly for phase- locked loop module, clock and data recovery module and a sending receiving module;Secondly, the main performance indicators of S ERDES chips such as transmission rate, bit error rate and jitter are introduced in detail, and the factors that affect them are analyzed. Again, the DFT technology in the SERDES chip is studied, and the paper introduces PRBS and LFSR, and the PRBS generation circuit and the verification circuit are used to realize the built- in self test, which plays the effect of the auxiliary chip test; Then use different simulation methods to do functional and physical verification of the digital circuit and analog circuit in SERDES chip,and do a test code coverage analysis for the digital circuit part;Finally,the paper studies the Ser Des chip testing scheme, and builds hardware PCB test platform with FPGA, then the chips is tested under various operating modes including interloop mode,outerloop mode and BIST mode,and the bit error rate is estimated.