Researches On The Key Technologies Of 2.5Gbps High-speed SerDes Circuit Based On 8B/10B Encoder And Decoder

With the development in processes of integrated circuits and diversity of process led to digital system scale growing continually. Also process size is already going from micrometer to nanometer, so integrated level of chip increasing continually. The requirement of communication speed is higher and higher. Now research is more focus on high-speed data transmission. So in the future, high-speed SerDes circuits will have more evolutionary space in field of semiconductor.This paper analyzed the current mainstream SerDes circuit architectures, including those based parallel clock embedded clock, bit interleaving and 8B / 10 B encoding and decoding of the SerDes circuit, focuses on the 8B / 10 B encoding and decoding SerDes circuit architecture, and its core key modules- including a charge pump phase locked loop circuit(PLL) clock and data recovery circuit(CDR) design were analyzed. Wherein the phase locked loop circuit comprises a low-pass filter, VCO, charge pump and phase frequency detector circuit modules, clock data recovery circuit comprises a frequency locked loop and phase lock loop frequency locked loop phase-locked loop circuit(PLL), a phase locked loop circuit module comprises a digital phase interpolation circuit, a phase detector and a phase selection circuit. TSMC 0.13?m standard CMOS process, the paper final design and implementation of a SerDes circuit layout area of 2433 um * 2505 um, experimental results show that the SerDes circuit can achieve data transfer rates 1.6-2.5Gbps output, it is possible to provide a 2.0Gbps the effective data bandwidth.In this article, we designed and achieved a high-speed SerDes that is a high-speed data interface circuit. It can provide flexible of other integrated chips. It has strong reusability an large utility and evolutionary space.