High-speed SerDes Transmitter Design And Implementation

With the rapid development of communication technology, the data transfer rate is getting higher and higher. The rate of data transfer has become a key bottleneck which is restricting the system performance, and thus how to achieve high-speed data transmission has attracted more and more researcher s. In the same time, IC process also keeps updating and progressing, the transistor speed is getting faster and faster, which makes the design of high-speed data transfer interface chip possible.In the field of high-speed data transmission, the serial link has gradually become the dominant instead of parallel link. First of all, the serial link can reach honger transmission distrance. Because the parallel link between each channel has serious crosstalk, it will influence the performance of the parallel link, and with the transmission distance increases, it will become more and more serious. Secondly, the serial link has a higher transmission speed. For the parallel link is a synchronous transmission, it need to synchronize the transmit clock signal. And because of clock distortion limit, the transmission speed can’t be too high. In addition, the serial data interface has fewer data ports, which simplifies the design of the interface chip significantly, and also reduces its area at the same time. It is precisely because of the above reasons, a growing number of transmission protocol using serial link, such as SATA、PCI-E、SONET. And most of the serial data need to convert from paralled, so the high-speed serial/parallel conversion interface(SerDes) came into being. IEEE 1394 communication network, also known as FireWire, is based on a high-speed serial bus that was developed to provide the same services as modern parallel buses.This paper presents a multi-rate transmitter that supports 4 data rates of 125 Mbps, 250 Mbps, 500 Mbps, and 1 Gbps. Its output meets the requirements of IEEE1394 B standard. Pre-emphasis is used in the transmitter to reduce inter-symbol interference(ISI) caused by channel low-pass effects. The design adopts Low-Voltage Differential Signaling(LVDS) driver with common- mode feedback(CMFB) circuit. In the fastest 1 Gbps data rate mode, the vertical eye opening of the eye diagram can reach 450 mV, while the jitter is only 38 ps.The chip is designed under 0.13 μm process, the area of the transmitter is20.67 *0.2 mm. The power consumption is 93.5 mW under 1 Gbps mode.