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Research And Design Of High Speed SAR ADC

Posted on:2017-01-27Degree:MasterType:Thesis
Country:ChinaCandidate:L QiFull Text:PDF
GTID:2308330488973401Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Wireless sensor networks (WSN) is widely used whether in the military or civilian areas. Analog to digital converter (ADC) plays an important part of WSN. During kinds of structures, successive approximation analog to digital converter (SAR ADC), with low power consumption and small area, can achieve higher resolution. Besides this, its sampling rate is also rising with the advancement of technology, therefore SAR structure has become the best choice of WSN. Meanwhile, SAR ADC has a wide range of applications in the field of portable instruments, industrial automation control and so on. As a growing amount of audio data, video and other multimedia information, WSN greatly increases the transmission rate requirements.This paper is based on the middle-high-speed WSN application to design a 50MS/s,12bit, low-power ADC using TSMC 0.18um CMOS process. The paper introduces common SAR ADC structures and adopts an improved segmentation capacitor fully differential structure. Bootstrapped switch structure with high linearity is adopted to improve the accuracy of the ADC. DAC capacitor array using a modified segmentation structure, which can reduce the total capacitance value and chip area, increase the capacitance matching, reduce power consumption and increase accuracy. High-speed dynamic comparator lowers static power consumption and satisfies the premise of the high-speed comparison. SAR control logic circuit improves the traditional synchronous timing circuit, effectively uses the idle time, reduces the delay and thereby improves the conversion rate. Completed the schematic design of the entire system, and circuit simulation results are as follows:the maximum sampling frequency can reach 79.4MS/s while ENOB is 11.71bit, SNDR of 72.28dB, SFDR is 81.37dB.In addition, the entire circuit layout is completed using TSMC 0.18um CMOS process and the layout area is 0.77mm2. The simulation results are as follows:the maximum sampling rate can reach 53.3MS/s while ENOB is 10.55 bit, SNDR is 65.27dB and SFDR is 74.1dB. The power consumption is 5.54mW at 1.8V supply voltage.
Keywords/Search Tags:Successive approximation ADC, Segmented capacitive structures, Fully differential structure, Improved timing synchronization
PDF Full Text Request
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