Design And Implementation Of Optical Phase-Locked Loop Control And Data Parallel Transmission System Based On FPGA

In recent years,with the rapid development in the field of space communications,coherent optical communication systems with faster transmission rate,larger transmission capacity and longer transmission distance have become the research hotspots.As the key technology,optical phase-locked loop technology has realized the synchronization between the phase of the input signal and the local oscillator signal,improving the sensitivity of the coherent optical communication system.With the vigorous development of digital signal processing technology,the complex and huge data transmission and processing are facing severe challenges in many fields such as radar signal processing,remote sensing data processing,quantum communication and so on.Because traditional single-path transmission uses only one path,it is easier to steal all the interactive information for attackers.As a result,the security of the system transmission is relatively poor.The data parallel transmission system uses multiple paths,and each path only transmits part of the data,which increases the difficulty of data being eavesdropped,and increases the security of the system.In this thesis,we focus on the two parts of optical phase-locked loop control and data parallel transmission,and study the optical phase-locked loop technology in coherent optical communication and the Ethernet data parallel transmission technology.The main work and innovations are as follows:(1)The optical phase-locked loop technology commonly used is studied in coherent optical communication systems.The structures and principles of the balanced phase-locked loop,decision-driven phase-locked loop,and Costas phase-locked loop are analyzed,and the advantages and disadvantages of them under different constraints are compared.(2)A subcarrier-based balanced optical phase-locked loop structure is improved.Based on the structure of sub-carrier balanced optical phase-locked loop,the frequency difference acquisition circuit is added to increase the bandwidth of the loop capture band.When the electric frequency difference signal is within a certain range,the frequency difference capture circuit will rapidly reduce the frequency difference between the local oscillator light and the signal light.When the frequency difference is reduced to a certain range,the phase locking function will be completed under the action of the loop filter circuit.(3)The feedback control algorithm of frequency difference is designed in the frequency difference acquisition circuit.The circuit constantly updates the dynamic voltage value by traversal search.After each update,the old and new frequency difference will be compared.By setting two frequency values as the threshold of the coarse adjustment and fine adjustment,and using the mechanism of changing the step size,the algorithm completes the feedback control of the frequency difference adjustment and achieves frequency locking.This algorithm shortens the frequency response time,greatly improving the stability of the optical phase-locked loop.(4)Based on the improved scheme of subcarrier balanced optical phase-locked loop,the experimental verification of homodyne optical phase-locked loop is realized.Based on the FPGA processing platform,a homodyne optical phase-locked loop experimental platform is set up to automatically capture the frequency difference in the range of 8GHz.The acquisition time is less than 1s and the frequency difference is stable within 1-3MHz,which further verify the feasibility of the experimental scheme.This result shows that the system has good stability and control performance.(5)The data parallel transmission scheme based on the physical layer is proposed.This system scheme is applied in the Ethernet environment.The data parallel transmission part adopts an adaptive scheduling algorithm based on transmission delay.The Ethernet frame is split and allocated to multiple physical channels for transmission based on this algorithm.The physical channels can be optical fibers,twisted pair,coaxial cables,etc.Each link in parallel uses the HDLC protocol for transmission.Receiver achieves data stream synchronization and reorganization through the data synchronization module.(6)Based on the proposed data parallel transmission scheme,the experimental verification of data parallel transmission module is realized.This experiment chooses Xilinx Kintex-7 series FPGA chip as the master chip and builds the experimental hardware circuit platform.The verification of the multi-path parallel transmission experiment adopts the LVDS signal interface.The feasibility of the system design is further verified through the test experiment and the simulation of each module.