Research And Realization Of Ultra-Low Specific On-Resistance LDMOS With Novel Field Plate

Realizing high breakdown voltage(BV) and low power consumption is the key target for the research of lateral power MOSFET devices. However, the BV and the specific on-resistance(Ron,sp) are in an undesirable Silicon Limit relation of Ron,sp∝BV2.5, as they both strongly depend on the drift doping concentration(Nd). For P-channel MOSFET, which has a lower carrier mobility, the issue is even more serious.In order to improve the BV and Ron,sp characteristics and achieve an excellent tradeoff between the BV and Ron,sp, a novel extended gate field plate with on-state accumulation effect(EG) is proposed. In the on-state, the EG induces high-density holes accumulation layer along the drift region surface, providing an ultralow-resistance conducting path. This accumulation-type current transport mode contributes to a much lower Ron,sp and makes the Ron,sp almost independent of the Nd, which greatly breaks through the Silicon Limit relation and improves the tradeoff between the BV and Ron,sp. In the off-state, the EG with a linearly doped N- region not only modulates the surface electric field distribution to enhance the BV, but also helps deplete the drift region to increase the optimized Nd and thus further reduce the Ron,sp. Additionally, the EG has a low leakage current, overcoming the drawback of the conventional resistive field plate.The novel EG structure is introduced into two P-channel LDMOS devices with different BV levels. Their mechanisms, characteristics and manufacturing processes are investigated in this thesis.1. With the EG structure and the REBULF technology combined, a 700V-level EG PFL pLDMOS device is proposed. Owing to the novel accumulation-type current transport mode, the enhanced depletion effect and the electric field modulation effect of the EG structure, the BV and Ron,sp characteristics are largely improved. Moreover, the P+ floating layer modulates the bulk field in the lateral and vertical directions, leading to an increase in the BV. Therefore, the EG PFL pLDMOS obtains a desirable static performance: the EG PFL pLDMOS increases the BV by 47%, decreases the Ron,sp by 68%, compared with the Con. pLDMOS. As for the dynamic performance, although the turn-off process of the EG PFL p LDMOS is longer than that of the Con. pLDMOS, but it contributes little to the switching loss. Thus, as a high-voltage device usually applied in medium or low frequency, the EG PFL pLDMOS shows no weakness in dynamic characteristic. At last, the manufacturing process and layout results are exhibited and some details in the experiment are analyzed.2. With the EG structure introduced into the basic RESURF structure, a 400V-level EG pLDMOS is proposed. As the EG pLDMOS does not need the P+ floating layer to enhance its verticcal BV, its structure and realization process are much easier. Compared with the N-top p LDMOS with Double-RESURF effect, the EG p LDMOS not only introduces the accumulation-type current transport mode but also enhances the depletion effect without affecting the current-conduting area; Furthermore, the EG structure with a linearly doped N- region has a better electric field modulation effect. Therefore, the BV and Ron,sp characteristics are remarkably improved: the EG pLDMOS increases the BV by 30.6%, decreases the Ron,sp by 61.8%, compared with the N-top pLDMOS. At last, the manufacturing scheme is designed.