A Simulation Study Of A Novel LDMOS With New Junction Termination

Lateral Double-diffused Metal-Oxide-Semiconductor Field Effect Transistors(LDMOSFETs) are widely applied to power integrated circuits. The high breakdown voltage and low specific on-resistance are both the key targets for the LDMOS. Nevertheless, there exists the contradiction of “Silicon Limit”(Ron,sp∝BV2.5) between the breakdown voltage and the specific on-resistance, which restricts the development towards the ideal power electronics. In order to break the Silicon Limit, two kinds of LDMOS are proposed in this thesis.1. A novel LDMOS with Junction Field Plate and N+ Floating Layer(JFP-NFL LDMOS). In the OFF-state, the JFP not only modulates the electric field distribution at the drift region surface, but also brings in the charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The N+ Floating Layer improves the vertical BV by introducing a reverse biased PN junction in the substrate. The JFP-NFL LDMOS reaches the BV of 712 V and Ron,sp of 77.7mΩ·cm2. Compared with the conventional LDMOS with the same dimensional parameters, the JFP-NFL LDMOS improves the BV by 55.8% and the Ron,sp by 45.2% according to the simulation results.2. A novel LDMOS with Accumulation-Effect Extended Gate(AEG LDMOS). In the ON-state, the extended gate accumulates electrons along the surface of the N-drift region, which provides a new current path and thus reduces the Ron,sp of the device. In the OFF-state, the extended gate not only modulates the electric field distribution at the drift region surface, but also brings in the charge compensation between the gate field plate and the N-drift region, which increases the doping concentration of the N-drift region. The AEG LDMOS reaches the BV of 707 V and Ron,sp of 40.3mΩ·cm2. Compared with the conventional LDMOS with the same dimensional parameters, the AEG LDMOS improves the BV by 54.5% and the Ron,sp by 72.1% according to the simulation results.Feasible fabrication process for the JFP-NFL LDMOS is designed and technological parameters are optimized as well. The layout is designed for further experiment.