New Structure Design And Simulation Research Of High Voltage SOI LDMOS Devices

SOI (Silicon On Insulator) technology has many advantages, including low leakage current, low parasitic capacitances, high switching speed, and ideal dielectric isolation between devices, so it is widely used in the smart power integrated circuit (SPIC) and high voltage integrated circuit (HVIC). For the high-voltage SOI LDMOS (Lateral Double-diffused Metal Oxide Semiconductor), the breakdown voltage (BV) is determined by the smaller values of the lateral breakdown voltage (LBV) and the vertical breakdown voltage(VBV). A long drift region will improve the LBV, but it will increase the specific on-resistance(Ron.sp). A thick BOX layer will improve the VBV, but it will enhance the self-heating effect(SHE). Several structures have been proposed to improve the relationship between the BV and Ron.sp, such as lateral field plates (LFP), reduced surface field (RESURF), super-junction (SJ)and trench-based technology.The main contents of this thesis are about to improve the relationship between the breakdown voltage and the specific on-resistance. The performance of the three proposed structures are validated using SILVACO device simulator. Specific research contents are as follows:(1) A split gate SOI trench LDMOSFET (SGT-LDMOS) structure is proposed and the low-resistance channel is introduced to further reduces the Ron.sp. The split gate SOI trench LDMOS with low-resistance channel (SGTL-LDMOS) structure shows a reduction in Ron.sp compared to that of a conventional SOI trench LDMOS (CT-LDMOS) and SGT-LDMOS structures. This is due to the increased N-type concentration in the drift region and the lower channel resistance. In addition, the split-gate floating structure in the SGTL-LDMOS also reduces the gate-charge (Qg) and increases the BV as compared to the CT-LDMOS. As a result,the BV of the SGTL-LDMOS increases from 183V of the CT-LDMOS to 227V, the Ron.sp decreases from 43.4 m?·cm2 to 9.3 m?·cm2, and the Qg decreases from 47 pC to 30 pC.(2) A novel multiple trench SOI LDMOSFET with Schottky rectifier (MTS-LDMOS) is proposed. The new structure is characterized by double oxide trenches and the Schottky rectifier is integrated between the two oxide trenches. Each oxide trench obtains a vertical field plate which enhances the depletion of the drift region and modulates the bulk electric field. As a result, the BV of the MTS-LDMOS increases from 293V of the conventional SOI LDMOS (C-LDMOS) to 345V, the Ron,sp decreases from 261.2 m?·cm2 to 120.1 m?·cm2 and the gate-drain charge (Qgd) decreases from 18 pC to 6 pC . Moreover, the reverse recovery time of the proposed structure shows a 60.6% reduction as compared to the C-LDMOS.(3) A novel SOI LDMOSFET with buried field plate (BFP-LDMOS) is proposed. The new structure is characterized by a double buried field plate which is surrounded by buried oxide layer (BOX) and connected to the source and drain electrode, respectively. The drain buried field plate (DBFP) prevents premature breakdown at the interface of the Silicon/BOX and enhances dielectric field. The source buried filed plate (SBFP) introduces a new electric field peak and modulates the distribution of the horizontal electric field. In addition, the BFP replaces part of the BOX, which is useful to minimize self-heating effects (SHE). As the simulation results, when compared to the conventional SOI LDMOS (C-LDMOS), the breakdown voltage (BV) in the BFP-LDMOS increases from 128 V to 182 V, the specific on-state resistance (Ron,sp) decreases from 20.5 m?·cm2 to 18.5 m?·cm2. Moreover, the maximum lattice temperature at the power of 1 mW/?m and Vgs = 10 V is depressed by 33.8 K as compared to the C-LDMOS device.