Study Of Conductance Enhancement High Voltage Power Devices

High breakdown voltage(BV)and low specific on-resistance(Ron,sp) are the key targets and research orientation of power devices design. However, a contradictory relation 2.5on,spR μBV exists between the BV and Ron,sp, which is known as the Silicon Limit.In order to break through the Silicon Limit and simultaneously overcome drawbacks of the conventional field plate technology, two novel low on-resistance lateral MOS structures featuring on-state accumulation effect are proposed. In the on-state, an accumulation layer of majority carriers is formed to build a continuous ultra-low on-resistance current path from source to drain. In the off-state, the extended field plate modulates the electric field distribution in the drift region so as to improve the BV. Owing to the mechanism mentioned above, the Ron,sp of the device depends on the accumulation charge density of the drift region instead of the doping concentration, so the compromise between BV and Ron,sp doesn’t have to be taken into account, which effectively alleviates the Silicon Limit 2.5on,spR μBV.Based on the mechanism mentioned above, two novel lateral MOS structures are proposed as follows:(1)An accumulation-type ultra-low specific on-resistance LDMOS with a U-shaped gate is proposed. Simulations show that the new structure can achieve a BV of 662 V and a Ron,sp of 12.4 m?·cm2. The BV increases by 88.6% and the Ron,sp reduces by 96.4% compared with those of conventional structure in the same size. In addition, owing to the transportation mechanism of the accumulation layer, the Ron,sp doesn’t depend on the doping concentration of the drift region. As a result, the highest figure of merit(FOM) is achieved when the BV gets the maximum. Therefore, the contradiction between BV and Ron,sp is largely broken. Combining the characteristics of U-shaped gate and accumulation layer, another deformation U-shaped gate lateral MOSFET is discussed to apply in lower voltage range. At last, the fabrication steps for the new structure are provided.(2)An extended gate thin SOI LDMOS is proposed. On one hand, this structure employs substrate etching technology to break through the vertical BV limit of SOI devices and avoid the linear doping in the drift region of conventional thin SOI device. On the other hand, the extended gate field plate induces an accumulation layer during the on-state and assists in depleting the drift region contributing to a higher doping concentration, which results in an obviously lower specific on-resistance. Simulations show that the novel structure achieves a BV of 695.6 V and a Ron,sp of 28.9 m?·cm2. Finally, according to the simulation results, the BV of the novel structure nearly linearly increases with the increase in the drift region length, and the doping concentration remains constant. Therefore, the novel structure broadens the application range of the SOI technology in high voltage area.