Reseach Of High Voltage LDMOS With Junction Field Plate

In order to pursue the high breakdown voltage(BV) and low specific on-resistance(Ron.sp), a new junction field plate(JFP) technology is proposed. The JFP not only keeps the advantages of the resistive field plate(RFP), which smoothes the surface electric field of the drift region, but also avoids the large leakage current which exists in the RFP. The JFP helps to improve the static performance of the lateral power devices significantly. We propose two kinds of LDMOS by applying the JFP to the LDMOS.1. A novel LDMOS with a JFP and a partial N-buried layer(REBULF). We propose the JFP-REBULF LDMOS by applying the JFP technology and the REBULF(REduced BULk Field) technology to the LDMOS which owns a thin epitaxial layer. The JFP not only modulates the electric field distribution at the drift region surface, but also brings in the charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The REBULF technology can improve the vertical BV by introducing a reverse biased PN junction in the substrate. The JFPREBULF LDMOS reaches the BV of 740 V and Ron.sp of 67.3mΩ·cm2. Compared with the conventional LDMOS with the same dimensional parameters, JFP-REBULF LDOMOS improves the BV by 67.4%, and reduces the Ron.sp by 45.7% simultaneously. The appropriate process flow and layout for the tape-out are designed.2. A novel LDMOS with a JFP. Sometimes, the lightly doped substrate is employed to manufacture the power device. Because the lightly doped substrate can sustain very high vertical voltage, the JFP technology is applied to the LDMOS directly, without the REBULF technology. The JFP structure increases the BV and reduces the Ron.sp of the JFP LDMOS. Without the REBULF, the fabrication of the JFP LDMOS is much easier than that of the JFP-REBULF LDMOS. The JFP LDMOS reaches the BV of 679 V and Ron.sp of 62.4mΩ·cm2. Compared with that of the conventional LDMOS with the same dimensional parameters, the BV is improved by 26.7%, and the Ron.sp is reduced by 66.4% simultaneously. The process flow for the JFP LDMOS is also designed.