Research Of Trench SOI LDMOS Devices Based On The Structure Of Floating Field Plate

With the proposal of“made in China 2025”in the 2018 NPC and the CPPCC,the role of integrated circuit in national development has become more and more important.As a kind of practical junction terminal technique in IC power device field,field plate technique is often applied in SOI LDMOS devices.By this way,not only using the advantages of SOI technique such as fast speed,low power consumption and good isolation,but also effectively improving the electric field and concentration distribution of device drift region.Then the withstand voltage and conduction properties are optimized.However,high breakdown voltage?BV?tends to call for drift region with greater length and lower concentration.While there is a special relationship between specific on-resistance(R_on,sp)and BV,R_on,sp inversely proportional to 2.5 square of BV,leading to bigger power consumption,that is what's called“Silicon Limit Problem”.This thesis aims at relieving the contradictory relation between BV and R_on,sp and two novel trench SOI LDMOS structures are proposed.The two proposed structures are trench SOI LDMOS with a floating vertical field plate and trench SOI LDMOS with symmetric dual floating vertical field plate,respectively.A trench SOI LDMOS with a floating vertical field plate?FVFPT SOI LDMOS?:A novel device is proposed by inserting a floating vertical field plate structure?FVFP?,which is connected with gate,into the oxide trench in drift region of the conventional trench SOI LDMOS?CT SOI LDMOS?via special connection method in non-working area of device.At the off state,the FVFP introduces a new electric field peak into drift region,leading to the promotion of withstand voltage and modulating the surface electric field of device.At the on state,owing to the assisted depletion effect of gate field plate,concentration of drift region is obviously promoted,which leads to the decreasing of R_on,sp.Ultimately on the premise of not sacrificing the BV of device,the conduction property is significantly improved.And introduction of FVFP decreases the temperature near drain side,improving the temperature property to a certain extent.The influences of structure parameters on the device performances are investigated by device simulation software.This thesis discusses a series of the parameters,such as concentration of drift region,location parameters of FVFP and structure parameters of FVFP impacting on BV and R_on,sp.Compared with the CT SOI LDMOS on the same top silicon layer of 7.5?m,drift region of 4.8?m and buried oxide layer of 0.5?m,R_on,sp of the FVFPT SOI LDMOS is reduced by 60.9%while its BV is kept the same value of 188V.A trench SOI LDMOS with symmetric dual floating vertical field plate?SDFVFPT SOI LDMOS?:Considering of limitation of modulating the electric field of the FVFPT SOI LDMOS.A novel device is proposed by inserting symmetric dual floating vertical field plate structure?SDFVFP?,which are connected with gate and drain respectively,into the oxide trench in drift region of the CT SOI LDMOS via special connection method in non-working area of device.At the off state,the SDFVFP introduces two new electric field peaks into drift region at the same time,leading to the promotion of withstand voltage and modulating the surface electric field of device more evenly,increasing the overall BV od device.At the on state,the gate field plate is like a junction terminate,which causes assisted depletion to surrounded drift region.But drain field plate restrains the depletion degree of gate field plate.So comparing with the FVFPT SOI LDMOS,SDFVFPT SOI LDMOS gets higher R_on,sp,however,lower than that of the CT SOI LDMOS.Ultimately,on the premise of increasing BV,the conduction property is also improved.The introduction of DSFVFP decreases the temperature near drain side,improving the temperature property to a certain extent.Moreover,partial temperature except drain side is also decreased compared with the FVFPT SOI LDMOS.The influences of structure parameters on the device performances are investigated by device simulation software,too.This thesis discusses a series of the parameters,such as the concentration of drift region,location parameters of SDFVFP and structure parameters of SDFVFP impacting on BV and R_on,sp.Compared with the CT SOI LDMOS on the same basis of top silicon layer of 7.5?m,drift region of 4.8?m and buried oxide layer of 0.5?m,BV of the SDFVFPT SOI LDMOS is increased by 27%and R_on,sp of SDFVFPT SOI LDMOS is reduced by 35%.And Compared with the FVFPT SOI LDMOS,SDFVFPT SOI LDMOS improves the withstand voltage and conduction properties simultaneously on the premise of not weakening the overall performance of device.