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Design And Process Analysis Of Novel SOI Devices With Ultra-low Specific On-resistance And High Voltage

Posted on:2017-05-10Degree:MasterType:Thesis
Country:ChinaCandidate:Y H ZhangFull Text:PDF
GTID:2308330485986449Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Power device is used in the wide yields, and the key issue is the power dissipation. The determinants are breakdown voltage(BV) and specific On-resistance(Ron,sp). The conventional ultra-thin SOI devices can improve the BV, but it generates a new problem, “hot spot”, caused by varied lateral doping, which has a bad effect on the reliability. Based on above, two novel ultra-thin SOI devices are proposed to improve the BV and reduce the Ron,sp, and their mechanism are investigated.1 、 An ultra-thin Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor(SOI LDMOS) device with accumulation-mode field plate is proposed. The main feature of the novel power device is that there is an accumulation-mode gate consisting of a PNP transistor above the drift region. In the Off-state, the P-region assists depleting the drift region, which can improve its doping concentration. In the On-state, an electron accumulation layer is formed, which offer a low resistance path. It not only reduces the resistance of the device, but also improve the distribution of the temperature on the drift surface. The results by simulation demonstrate that the Ron,sp of novel device is 21.1mΩ?cm2, approximately one fifth of the conventional ultra-thin device keeping the same BV. Besides, at the same power, the highest temperature of conventional device is 415 K, while that of the novel device is just 344 K. At last, two processes are proposed to produce the novel device.2、An ultra-thin SOI LDMOS device with low specific on-resistance and high breakdown voltage is proposed. An accumulation-mode extended gate(AG) and backside etching(BE) are the features of novel device, and the doping concentration of its drift region is uniform. The extended gate consists of a P- region and two diodes in series. In the on-state with VGD>0, due to the AG, an electron accumulation layer is formed along the drift region surface, which forms an ultra-low resistance current path and thus reduces the specific on-resistance. What`s more, the novel device can obtain a lower temperature distribution compared with the conventional device. In the off-state, the AG modulates the surface electric field distribution, improve the lateral breakdown voltage. What`s more, the BE technique not only avoids vertical premature breakdown absolutely but also avoids the variable lateral doping(VLD) and the “hot-spot”. Besides, it improve the heat dissipation ability. In simulation, the breakdown voltage of novel device is 818 V, the specific On-resistance is 38.1mΩ?cm2, reduced by 70.2%. At the last, to produce the novel device, the paper proposes two processes, which is easier than the processes of the former.
Keywords/Search Tags:accumulation-mode field plate, LDMOS, breakdown voltage, specific Onresistance, temperature
PDF Full Text Request
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