Design And Technical Realization Of LDMOS With Novel Temination

Power LDMOS devices are applied widely in power ICs because the advantages of easy integrated and fast frequency response. Low power dissipation is the further direction of power devices, the breakdown voltage(BV) and specific on-resistance(Ron,sp) decide the turn-off power dissipation and conduction dissipation, respectively. So high BV and low Ron,sp are the important design target of the power LDMOS. However, Intense contradiction exists between BV and Ron,sp in high voltage field, that’s the “Silicon Limit” in Semiconductor Industry.Focusing on “Silicon Limit”, combining some familiar junction termination techniques(RESURF, Field Plate, REBULF), this thesis proposes and investigates two kinds of novel termination p-channel LDMOS devices. Based on the structures, the feasible process and layout are designed.(1) A novel p LDMOS with junction Field Plate and REBULF structure is proposed, the manufacture process and layout are designed on the basis of the process platform. First, the JFP above the drift region surface Significantly improves the electronic field distribution of the drift region, then enhances the BV; at the same time, the impurities in the JFP and the drift region deplete each other, the doping concentration of drift region is increased, consequently, the Ron,sp is decreased. Secondly, the N-type buried layer below the N-body region plays a role of RESURF, it can reduced the electronic field near the main junction and further reduce the Ron,sp. Thirdly, the P-type floating layer is a REBULF structure, it introduces two reverse P+N diodes, the diodes improve the vertical electronic field under the drain and the lateral electronic field near the source, respectively, thus enhance the BV. According to the device simulation and process simulation, we optimize the parameters of the JFP-REBULF pLDMOS device. The optimized BV and Ron,sp are 752 V and 312mΩ·cm2, respectively. Based the simulation results, the layout is designed and the device is manufacturing in progress.(2) a novel SOI p LDMOS with accumulation extend gate field plate structure(AEG SOI pLDMOS) is proposed. The device features an AEG above the drift region surface, and the both sides of the AEG are connected with the gate electrode and drain electrode, respectively. In the conduction state, the potential on the AEG induces high concentration holes accumulation layer at the drift region surface, the holes accumulation layer greatly reduces the device Ron,sp; in the reverse state, the AEG modulates the electronic field distribution of the drift region, thus improves the BV. Simulation results show that, the BV is 318 V and the Ron,sp is 11.8mΩ·cm2 with 20μm cell pitch. Compared with conventional SOI pLDMOS at the same cell pitch, the BV of the AEG SOI pLDMOS is improves by 40.5% and the Ron,sp of the AEG SOI pLDMOS is reduced by 74.6%. based on the device characteristic, the feasible process project is designed.