Research And Optimization Of Voltage Endurance Characteristic Of SiC LDMOS

With the development of power electronics and the increasing global demand for energy,the development of high-power semiconductor devices has become particularly important.As a wide band semiconductor material,silicon carbide(SiC)is widely used in high voltage power semiconductor devices with high critical electric field and high thermal conductivity.SiC based laterally diffused metal oxide semiconductor(LDMOS)is an important power device,whose property optimization has been a hot topic of research.However,as the performance of SiC LDMOS devices continues to improve,voltage endurance remains a bottleneck factor that restricts its application.The purpose of this thesis is to optimize the voltage endurance characteristic of SiC LDMOS.The theoretical analysis of device structure and process parameters on voltage endurance characteristic is combined with simulation results to obtain systematic conclusions and optimization methods,aiming to improve the voltage endurance capability of the device.The main contents of this thesis are as follows:According to the basic theory of SiC LDMOS,the equations for important electrical characteristics,including breakdown voltage,on-resistance,and threshold voltage were deduced.Additionally,the main factors that affect changes in these parameters were analyzed.Based on SiC material,the LDMOS device structure,process parameters and physical simulation models were established.Finally,voltage endurance simulations were conducted on conventional SiC LDMOS(C-LDMOS),SiC LDMOS with a P-top layer(P-LDMOS),SiC LDMOS with the trench structure(T-LDMOS),and SiC LDMOS with multi-field limiting ring structure(MR-LDMOS).The principle analysis of various factors affecting the voltage endurance characteristic were analyzed and optimization suggestions were proposed.According to the simulation results,the following conclusions can be drawn:(1)In C-LDMOS,decreasing the doping concentration in the drift region,enlarging the length of the drift region and increasing the thickness of the gate oxide layer can all enhance the voltage endurance.However,increasing the drift region length has a maximum value for improving the breakdown voltage.Reducing the doping concentration in the drift region will increase the specific on-resistance.Increasing the thickness of the gate oxide will lead to an increase in the threshold voltage.The specific on-resistance and threshold voltage can be reduced by appropriately reducing the doping concentration in the P-body region while ensuring the voltage endurance of the device.(2)In P-LDMOS,the introduction of P-top layer structure increases the breakdown voltage significantly.With the increase of P-top layer length,doping and junction depth,the breakdown voltage of P-LDMOS increases first and then decreases,and the specific on-resistance continues to increase.The depletion effect of P-top layer improves the voltage endurance of the device drift region and balances the surface electric field distribution.The breakdown voltage increases,but the drain electric field increases accordingly.To prevent premature breakdown of the device,the above parameters should be adjusted appropriately to optimize the voltage endurance of the P-LDMOS.(3)In T-LDMOS,the introduction of trench structure increases the length of drift region and the breakdown voltage increases significantly.With the increase of trench width and depth,the breakdown point of the device is transferred to the edge of the trench with higher voltage endurance and the current path is compressed when the device is on.The breakdown voltage of T-LDMOS first increases and then decreases with the increase of trench width and depth,and the specific on-state resistance increases persistently.The optimization of the breakdown voltage by the trench depth is greater than that by the trench width.Reasonably increasing the depth of the trench and decreasing the width of the trench can improve the voltage endurance of the device and reduce the specific on-resistance.(4)In MR-LDMOS,linear ring spacing design is better than equal ring spacing design.With an increase in the number of the field limiting rings,more electric field peaks are introduced on the device surface to balance the electric field distribution.As ring gets closer to the drain,the device eventually breakdown at the drain.The breakdown voltage of MR-LDMOS increases first and then decreases,and the specific on-resistance increases continuously.The ring doping concentration increases,the surface electric field of the device tends to flatten out,and the breakdown voltage achieves its peak value when the electric field intensity of the source and drain terminals are the same.With an increase in the depth of the ring structure,the breakdown voltage first increases and then decreases,and the doping concentration of the drift region corresponding to the highest breakdown voltage increases.When the doping concentration in the drift region is high,the number of failure field rings is greater with smaller ring doping concentration and depth.In summary,A simulation analysis of the process parameters and optimized structure of SiC LDMOS are presented in this thesis,and based on the results obtained,optimized the design,significantly improving the device’s voltage endurance capability.It has a certain reference value for the research and application of SiC LDMOS in high voltage field.