Research Of Novel High Voltage SOI D-RESURF LDMOS Devices

Silicon on Insulator (SOI) High Voltage Integrated Circui (HVIC) attracts a great number ofattentions due to the merits of good isolation, high integrated density, fast respond speed andimmunity to radiation. And RESURF and field plate (FP) technology is the most importanttechniques for lateral power devices. Double RESURF (D-RESURF) technology can improvedevices breakdown voltage and can decrease their On-resistance obviously. In this thesis, two novelSOI LDMOS structures are proposed to meet those features, and are investigated from the basiccharacteristics and fabrication process with the TCAD tools.Firstly, the SOI D-RESURF LDMOS with P+region is proposed. The device structure ischaracterized by a heavily-doped P+region which is connected to the P-top layer in the drift region.By researching the basic characteristics in use of the MEDICI software, the results show that thisnew structure effectively improves the surface electric field, and presents a high breakdown voltage,increase by5%, a low specific on-resistance, decrease by25.8%, and can reduce the sensitivity ofthe performance on the device parameters, thus resulting in the flexible design and fabrication. Then,a process CMOS-compatible process is proposed to fabricate the P+P-top SOI D-RESURF LDMOSdevice. The process conditions and parameters are optimized by using the Silvaco Athena.Secondly, the SOI D-RESURF LDMOS with floating field plate is proposed. The devicestructure is characterized by a field plate above the positive-biased PN junction near the channelwhich is without any electrical connection and bias voltage. By researching the basic characteristicsin use of the MEDICI software, the results show that this new structure effectively improves thesurface electric field, and presents a high breakdown voltage, a low specific on-resistance.Compared to the conventional SOI D-RESURF LDMOS device, a5%increase in breakdownvoltage and a25.5%decrease in specific on-resistance can be obtained in the novel device. Then theinfluence of the P-top layer parameters on the device breakdown voltage and specific on-resistenceis studied, the results show that the novel FFP SOI D-RESURF LDMOS device reduces thesensitivity of the breakdown voltage and specific on-resistence on the device parameters and resultsin the flexible design and fabrication. Finally, a process CMOS-compatible process is proposed tofabricate the FFP SOI D-RESURF LDMOS device. The process conditions and parameters areoptimized by using the Silvaco Athena.