Design Of High-speed Low-power Pipeline ADC

The project is aimed at designing a high-speed low-power pipeline ADC with 65 nm CMOS technology. To achieve high-speed and high-accuracy, the bootstrapped switch and a one-stage op amp with a gain of 10 is used in this design, together with calibration algorithm, the performance of ADC is greatly improved.A 4-bit SHA-less front-end architecture is adopted in this design, because it is hard to design a high gain op amp with short channel devices, thus a SHA circuit will not be used while design a high-speed high-accuracy ADC. SHA-less architecture will make it harder to design a high linearity switch, often a bootstrap switch is a must.The sampling rate of a high-speed low-power is decided by bandwidth of op amp. The Eigen frequency of 65 nm CMOS device is about 100 GHz, so the bandwidth will be enough for our design with a low gain op amp of 10.The calibration algorithm is presented after introducing the capacitor mismatch, offset error and gain error, and removes the capacitor mismatch and gain error. As for offset error, the pipeline ADC can calibrate it itself. Attention should be paid that the calibration algorithm is based on the high linearity of op amp, so it should be carefully designed.The left-right floor plan is used after considering three types of layout floor plan. With symmetry at top level design becomes more and more popular these years; this layout is designed mirror symmetrically.Realized in 65 nm CMOS technology, the ADC performance can meet our design purpose. The pre-simulation results show it can achieve a figure of merit of 221fJ/step while post-simulation 298fJ/step and the ENOB can up to 9.82-bit and 9.39-bit separately.