The Design Of Low Power Pipeline ADC For High Definition Digital Video

In recent years,electronic system almost all realized digitizing.But in the nature,Signal still exists in the form of analog,therefore,we need a medium to translate the analog signals into digital signals,we call it ADC.ADC which is the bridge between digital and analog is applied in many areas,especially in digital signal processing?radar signal analysis?medical imaging equipment?and multi-media equipment etc.This article is based on the background of high-definition digital video display.High-speed?high-resolution?low-power ADC is the reflect of advanced technology and development trend in the future?The structure of ADC has flash ADC?SAR ADC?pipeline ADC and delta-sigma ADC.on account of the Pipeline ADC has a compromise in accuracy?speed?area and power consumption,it can be well applied to digital communication systems and high-definition video display system.With the CMOS technology developing,the characteristics of the transistor size is shortened,the transistor speed power consumption and other performance indicators continue to improve,the traditional design methods and structure can not meet the demand,As a result,digital calibration technology came into being.High-speed and high-resolution low-power ADC is the research topic of This paper.The structure and performance requirements of the pipeline ADC are analyzed.The overall structure of the pipeline ADC is determined on the analysis of speed?accuracy?area and power consumption.And applying digital calibration on-chip to correct the errors in the design process to reduce power consumption and the area of chip.The design of circuit module?digital calibration?pre-simulation?post-simulation have been done.A prototype of the ADC is fabricated in SMIC 55 nm CMOS technology.A ENOB of 9.86 bit after calibration is achieved at a sampling rate of 200 MSPS with 91 MHz input,while consuming 68 mW from a 1.2 V supply.