Research And Design Of 12/14 Bit High Speed Pipeline A/D Converter

In recent years, with the development of 3G mobile communication, great demands have been growing for the analog-digital interface circuits, especially ADC. ADC technology has developed at the same time toward high speed high definition. As is to now, the fastest ADC reaches 40GS/s, while the highest definition the ADC is 31bit. All kinds of ADC fulfill the applications of high definition TV and handsets.In this dissertation, a design of a 12bit pipelined ADC is presented with applications in wireless communication transceiver and high definition TV. The work of this dissertation includes the following. First, analyze the pipelined 1.5bit/stage algorithm and its realization. Second, explore several non-ideal parameters and their effects on the ADC system, then give a few approaches to kill these errors. Third, do system simulation of 12bit ADC using Simulink behavior level model. Forth, design a special 1.5bit pipeline stage. A two stage high gain amplifier is as the core of the pipeline stage. Self gain boost switches are placed at the input of the pipeline stage to provide high linearity. Fifth, dynamic biasing circuit adjusts the reference voltage and current with the sampling clock. In this way, a lot of power is saved. Sixth, simulate the whole ADC in TSMC 0.35μm Logic technology and tape out the chips. Test is done with 10MHz sine input @100MS/s. Result shows SFDR=73.23dB, SNR=62.75dB, power=113mW, INL 1.5LSB, and DNL=0.25LSB. The area of the chip is 0.93mm~2.The last part of the dissertation is based on the design of the 12bit pipeline ADC chip and discusses the main difficulty in realizing 14bit high resolution ADC. Capacitor mismatch error averaging (CEA) technology is utilized to solve this problem. A pipeline stage with CEA is presented.