Design And Implementation Of Turbo Decoder For Communication Accelerator Based On LTE Protocol

With the commercialization of LTE, the traditional mobile communication network has encountered great difficulties and challenges in response to the requirements of high bandwidth and high real-time performance of LTE system. To cope with these challenges, China Mobile proposed the C-RAN network in 2009. In the deployment of C-RAN network, we need the communication accelerator and other special hardwares to assist its processing.In this paper, I do some research on the turbo decoder of the communication accelerator and focus on the turbo decoder’s design and implemention, which is based on the LTE.Firstly, I analyze the turbo coder.Then, I study three decoding algorithms(MAP algorithm, Log-MAP algorithm and MAX-Log-MAP algorithm) and their principle, calculation complexity and decoding performance. Finally, considering the performance and complexity, I select the MAX-Log-MAP as the algorithm for hardware implementation.In order to improve the performance of turbo decoding and reduce the decoding delay, this paper does some research on several decoding key technologies. Firstly, a parallel architecture of SISO decoder is presented, and I analyze the influence of different parameters on the final decoding performance. The results show that the performance of this decoding structure is better than that of the traditional structure. Secondly, this paper analyzes the parallel decoding structure and sub block pipeline sliding window algorithm, analyzes the influence of different block numbers, and deduces the Radix-4 algorithm. Next, the non conflict parallel QPP is analyzed, and the calculation process is simplified. Then, different iterative stopping criterions are analyzed, and the parallel HDA criterion is proposed.Finally, the Matlab fixed-point simulation of the algorithm is carried out.In this paper, I design the turbo decoder for communication accelerator and implement it on the FPGA. Firstly, the system architecture and the top interface of the turbo decoding communication accelerator are analyzed. Secondly, I analyze the interface of each sub module, emphatically analyze the structures of the rate dematching module and turbo decoding module and the detail design of some modules, and give simulation in Modelsim. Then, I simulate the entire module by Modelsim.At last, I test the designed circuit in Altera Stratix V(chip: 5SGXEA7K2F35C2), and the association test of turbo encoding and decoding of the communication accelerator is carried out. Finally, the resource consumption of the whole module and some performance indexes are given.In this paper, all the functions of the communication accelerator of the Turbo decoding are realized, including the rate dematching and Turbo decoding. Combined with the communication accelerator of Turbo encoding, it can be very good to assist the general processing platform to deal with the turbo coding and decoding work.