Design And FPGA Implementation Of Turbo Code For LTE Systems

Turbo code has attracted great attention for its excellent performance close to the Shannon limit. Now,Turbo code has been applied to many kinds of modern communication systems successfully such as the 3rd generation moble communication,satellite communication and digital-video-broadcasting system. And the 3GPP has selected Turbo code as one of the channel coding scheme for the LTE and LTE-A system in future to meet the requirement of high datarate communication. This paper researchs high-speed decoding algorithms and its implementation in hardware for Turbo code in LTE systems with low complexity.This paper first introduces the principle of encoding and decoding for Turbo code, and analyses the performance of general decoding algorithms such as: MAP algorithm, LOG_MAP algorithm, MAX_LOG_MAP algorithm and several improved algorithms. To reduce the decoding delay and improve the throughput rate effectively, for algorithm aspect, this paper researchs the HDA stop iterative criterion and the Radix-8 algorithm which deal with three bits per clock cycle; for structure aspect, this paper first introduces the serial decoding structure based on the pipeline structure,then emphatically analyzes the parallel decoding structure and the sub-block pipeline sliding window algorithm. In additon,the principle for designing parallel CT interleaver is given in this paper.Finally, this paper shows the FPGA design schemes for Turbo code in LTE systems. By using ISE platform and Kintex-7 chip from Xilinx, the author finished the hardware implementation for Turbo encoder and decoder in LTE systems. After debugging and optimization seriously, the decoding performance meets the requirements of systems.