Design And FPGA Implementation Of Memory Reduced Turbo Code Decoder Based On Reverse Butterfly Calculation

Turbo codes have become an important research topic in the field of channel coding and were widely used in wireless communication,due to their decoding performance close to Shannon's limit.Nowadays,Turbo codes have been selected as the channel coding scheme by the LTE-Advanced standard.It has also been applied to the Internet of Things,encrypted transmission of images,and deep space communications.In the hardware implementation of the turbo code decoder,the decoder usually uses an iterative decoding algorithm for decoding.The storage unit will be accessed frequently during the decoding process,which will cause a large loss of power.Among them,the power loss caused by accessing the state metric cache(SMC)accounts for more than half of the overall power consumption of the decoder.Therefore,the power consumption of the Turbo code decoder becomes an important issue in the energy-constrained wireless communication systems.In order to address this problem and satisfy the requirements of low-power wireless communication systems,the decoder of a memory reduced has become an essential topic.This thesis adopts Turbo code in the LTE-Advanced standard as the research content.Firstly,the encoding method and decoding principle of Turbo codes are introduced.Secondly,the maximum a posteriori(MAP)algorithm and its improved algorithms are theoretically derived and analyzed.Then,using the design idea of changing the storage mode of state metric,the decoding scheme based on the linear estimation is proposed.In this scheme,a sorting module and an increment calculation module are inserted into the traditional structure to calculate the increment bits and position bits.At the same time,these bits are stored without the need to store forward state metrics.The results showed that the SMC capacity decreased by 55%.In the above the design of Turbo code decoder structure,although the capacity of SMC has been reduced,it can be further decreased.Moreover,in the above scheme,due to excessive compression of state metrics,this will reduce the performance of Bit Error Rate(BER)and Packet Error Rate(PER).In addition,the decoding structure cannot be fully implemented in parallel.Therefore,using the design idea of the reverse calculation,the decoding scheme based on reverse butterfly calculation is proposed in this thesis.In this scheme,the traditional trellis diagram of Turbo codes is divided into four independent butterfly units.Instead of storing all forward state metrics,only sign bits and state metrics that cannot be recalculated are stored.The results showed that this scheme reduces the SMC capacity by 65%,and the performance of BER and PER is very close to that of the maximum a posteriori probability algorithm in logarithmic domain(Log-MAP).Finally,in the thesis,the decoder architecture is further studied and discussed based on reverse butterfly calculation.Then the design scheme of the decoder is realized by using Verilog Hardware Description Language(HDL)in the Quartus II 13.0 software platform.Meanwhile,the PowerPlay Early Power Estimator and ModelSim are used for power measurement and decoding time analysis.The results show that in terms of hardware overhead,in comparison to the traditional decoder structure,the total memory of the decoder structure is reduced by 35.62%.At the frequency of 200 MHz,the total power consumption and decoding time is decreased by 15.38% and 45.45% compared with the traditional decoder structure and the linear estimated decoder structure,respectively.Therefore,the Turbo code decoder designed in this thesis can effectively reduce the power consumption and maintaining better decoding performance.