Research And Implementation Of High Performance Turbo Decoder

Error Correction Code (ECC) is one of the key technologies that improve the reliability of the communication system and the usage of the frequency resources. As one of the best Forward Error Correct (FEC) codes whose performance are close to Shannon limit, Turbo codes have been widely used and researched since it’s introduced. Turbo codes have been adopted by most communication standards such as mobile communication, deep space communication, multimedia broadcasting and power line communication. The4G mobile communication standard LTE-Advanced and WiMAX-Advanced also adopt Turbo as their channel code.The requirement on the capacity, speed and power efficient of communication for the next generation are becoming higher and higher. Besides various communication standards are developed and used. As a result, there are two current for the Turbo decoder design:1) Design a decoder with high throughput, low power consumption and low cost;2) Design a flexible and reconfigurable decoder that can support various standards. The main goal of this paper is to improve the throughput and configurability of the decoder while reduce the complexity and memory requirement. To achieve this goal, the decoding algorithms and architectures are optimized in this paper.The main work and contribution of this paper include:1) To reduce the decoding latency of architectures with high parallel, the traditional sliding-window decoding schedule is adjusted and the decoder can do the forward recursion and backward recursion at the same time. Besides we pass the boundary state metrics between neighbor iterations. In this way, we reduce the decoding latency and increase the hardware usage and throughput of the decoder;2) A new architectures with high radix is proposed. By comparing the embranchment that have the same starting and ending state in the grid map in advance, the complexity of the recursion unit and the critical path are reduced;3) A simplified interleaver for decoder with high parallel and high radix is proposed. It makes the interleaver for LTE and WiMax can be simply developed based on barrel shifting network and tw0-dimensional address generator;4) The storing architecture is optimized. By this optimization, we avoid the memory access collision and the memory bits and numbers of memories needed are also reduced;5) The operation complexity is also reduced by the optimization of decoding algorithm and the resource sharing.To verify the proposed techniques in this paper, two Turbo decoders have been developed:Decoder-I and Decoder-II. Decoder-I is a radix-4decoder with a parallelism of32and can support both LTE and LTE-advanced standards. Based on SMIC0.13μm1P8M CMOS technology, it’s verified by post-layout simulation. Decoder-I occupies12.24mm2core area and can operate at285MHz. The max throughput is1.52Gbps with5.5iterations. Decoder-II is a radix-16decoder with a parallelism of4and can support both LTE and WiMAX standards. It developed on TSMC65nm1P9M LP CMOS technology and has been taped out. The core area is1.39mm2and the maximum operating clock frequency is600MHz. With5.5iterations, the max throughput is821Mbps in LTE and810.6Mbps in WiMAX.