The Research And Design Of High-Speed High-Precision Analog-To-Digital Converters

High-speed high-resolution analog-to-digital converters(ADCs) are critical building blocks in many electronic applications, representing the most advanced technology and the development trend in the future. For its great value in the high-end military and civilian fields, such as high-speed mobile communication(3G/4G), radar systems(phasearray radar), aerospace avionics, multi-input multi-output systems, IC industrial tycoons and universities and research institutions have made great efforts to study high-speed high-resolution ADCs. When a high-speed high-resolution ADC is used in the system, intermediate frequency blocks(mixers, synthesizers, amplifiers, filters, etc.) can be drop out, which simplifies the system structure and reduce power, size and weight.Various architectures – folding, pipeline, time-interleaving – have been used to deliver these high-speed high-resolution ADCs. Of these, pipeline architecture has proven to be the most efficient for applications such as digital communication systems and video systems. While generic issues such as capacitor mismatch provided the obstruction in early pipelined ADC design, deep-submicron low-voltage technologies have made it increasingly difficult to realize high-gain op amps, requiring additional digital calibration that corrects for gain error.Based on the extensive study of the trade-off between speed, resolution and power, optimized capacitor scaling factor and resolution division is found in this research. A foreground pipelined ADC calibration technique that allows the use of high-speed and yet inaccurate op amps is adopted, and background calibration is also implemented to trace the environmental change. A Simulink behavioral model of pipelined ADC incorporating foreground and background calibration has verified the effectiveness of the calibration algorithm. A 10 bit 500MSPs pipelined ADC under TSMC 65 nm is designed and it achieves 9.4bit ENOB with a 250 MHz, 1.2V full-scale input after calibration, while consuming 16 mW if only analog blocks are considered.