Research On Key Technology Of High-speed Two-step SAR Analog-to-Digital Converter

With the rapid development of the wireless communication field,mobile wireless networks have entered the 5G era from the 3G era to the 4G era.With the birth and development of new communication technologies,the requirements for analog-to-digital converters(ADCs)at the signal receiving end are getting higher and higher.Nowadays,the sampling rate of the analog-to-digital converters is required to reach GS/s or higher.The demand for low-power high-speed,medium-resolution analog-to-digital converters is also increasing.The successive approximation analog-to-digital converter(SAR ADC)has become a popular research direction in the medium and high speed field due to its low power consumption,small area and simple structure based on high speed.The two-step SAR ADC based on the SAR ADC can maintain the advantages of the SAR ADC with low power consumption and small area on the basis of high speed,and is suitable for use in the field of high speed and low power consumption.This thesis first elaborates and analyzes the specific architecture and working principle of SAR ADC,and proposes a variety of new high-speed and low-power SAR ADC structural modules,including bootstrap switch structure,two-stage dynamic comparator structure,and new SAR control logic structure,asynchronous clock CLKC generation structure.And design the sampling clock and switching clock generation structure of the high-speed ADC.Finally,the speed of the single-channel SAR ADC is improved and its power consumption is reduced.Then based on the structure of a high-speed and low-power single-channel SAR ADC,a two-step SAR ADC with a new architecture is proposed.In this article,the specific structure of the two-step SAR ADC designed this time and the corresponding working principle are described in detail.The analysis and comparison of the pros and cons of the active transmission margin and the passive transmission margin in the two-step ADC are compared.Describes a new type of margin transmission-amplification mode.Analyze the structure and design ideas of the new comparator used in the two-step SAR ADC proposed in this paper,and analyze the noise of the comparator.Restudy and analyze the impact of clock jitter on ADC performance,and ensure that the clock jitter of the designed sampling clock meets the design requirements.Finally,the high-speed,low-power ADC performance requirements are met.The prototype was fabricated in TSMC 28 nm and standard CMOS process to realize an8-bit 1.5GHz two-step SAR ADC.The post-simulation results show that when the number of sampling points is 1024,the sampling frequency of the two-step SAR ADC is 1.5GS/s.When the frequency of the input signal is 745.605 MHz,when the frequency of the input signal is close to the Nyquist frequency,SNR is 48.7d B,and the SNDR reaches 48.6d B without spurious SFDR reaches 69.3d B,and the ENOB reaches 7.78 bits from a single1.8V supply.The power consumption of the chip is only 1.3m W.