Design Of Folding ADC For Wireless Communication System

The continuous improvement of wireless communication systems put forward higher requirements on ADCs. High speed and medium resolution ADCs are widely used in this kind of systems. With the increasing speed of communication, the sampling speed of ADC has become a major bottleneck to limit the system speed. In order to achieve higher speed sampling, folding and interpolation ADC has a smaller power consumption compared with the conventional parallel ADC, therefore has become the mainstream of the structure of high speed ADCs. However, single ADC can only achieve limited sampling speed due to their process. In order to further increase the sampling rate, multi-channel time-interleaved technology is used to make the speed increased exponentially and breakthrough the process limit. Folding and interpolation ADC with time-interleaving technology in wireless communication systems will become the mainstream in the future.Aiming at the development trend and characteristics of wireless communi cation system, this thesis designs a 4-channel time-interleaved ADC based on the 65 nm CMOS TSMC technology. ADC realizes the sampling rate of 2GSps, the effective resolution of 7.86 bit, and the design goal is achieved.First of all, this thesis introduces the key performance parameters of ADC design and explains the meaning of each parameter in detail, so as to evaluate the performance of ADC. Secondly, analyze the working principle of multi-channel time-interleaving technique and analyze the three main error sources in the frequency domain by Fourier transform, namely inter channel offset mismatch, inter channel gain mismatch, and inter channel timing mismatch. On this base, the influence of various errors on the dynamic performance of ADC is estimated, and a kind of mixed-signal calibration algorithm based on statistical properties is introduced. Thirdly, the principle of folding and interpolation is explained in detail, the parallel folding and cascade folding are introduced, and the main error sources of the folding and interpolation circuit are analyzed. At last, it introduces the various modules of the circuit. It analyze the input-dependent clock feedthrough in conventional bootstrapped switch, proposed a new kind of capacitor compensation network, and simulation results show that this new compensation method can effectively suppress the pedestal error caused by clock feedthrough effect. It analyze the folding and interpolation circuit, 32 folding and interpolating curves are generated by simulation, the function of the folding and interpolation is verified. The encoding and bit synchronization logic is derived, the bubble correction module is introduced into the encoding circuit, and the dynamic simulation of the whole ADC is completed.