| In nuclear and particle physics experiments, the waveforms of the pulse signals generated by detectors carry the most comprehensive and detailed physical information. Many experimental physicists in the world have been trying their best to find an effective method to obtain the waveforms of the pulse signals generated by particles. However, the technology of the Analog-to-Digital Converter (ADC) has become a bottle-neck. Hence, to break through the limit of the ADC’s sampling rate with a given resolution, it is very important to develop the parallel ADC architectures. In this dissertation, we focus on the designs and implementations of two time-interleaved based parallel ADC system (TIADC), which are ultra-high-speed (10Gsps and8-bit) ADC system and high-speed high-resolution (1600Msps and14-bit) ADC system respectively. Due to the well-known reason that the time-interleaved technique brings the channel mismatch errors, which cause the so-called pattern noises and significantly degrade the dynamic and static performance of the TIADC system, the mismatch errors correction becomes an essential part of the TIADC system. To realize a real-time correction of the high-speed high-resolution TIADC system, a new correction method named parallel multichannel-filtering approach, which is based on the poly-phase realization of the perfect reconstruction filter banks method, is proposed in this dissertation.In chapter1, we first introduce the development, the urgent needs and the difficulties of the waveform digitization technology employed in the particle physics experiments, and then present the time-interleaved technique which can be used to break through the limits of a single ADC chip.Chapter2includes the review of the sampling theory and ADC theory&performance, the detailed introduction of two different architecture ADCs ultra-high-speed flash ADC and high-speed high resolution Pipeline ADC, which are used in the two TIADC systems.First, the common sampling techniques are presented in chapter3, and then the time-interleaved technique is introduced in detail, including the analysis and simulation of mismatch errors.Based on the theory presented in the chapter3, general hardware architecture of high-speed high-resolution TIADC system is introduced in chapter4, and then we discuss the difficulties and challenges faced in the implementation of high-speed high-resolution TIADC systems. At the end of chapter4, the parallel multichannel-filtering approach is proposed and corresponding simulations are done to verify it.In chapter5and6, we introduce the designs and implementations of a14Bit1600Msps high-speed high-resolution TIADC system and an8Bit10Gsps ultra-high-speed TIADC system respectively. We focus on the multi-phase clock, the analog input signal splitting, high-speed parallel data receiving and buffering, the implementation of the parallel multichannel-filtering approach in the FPGA, commands and data transfer interface and power and thermal considerations, especially the implementation of the parallel multichannel-filtering approach in the FPGA.To evaluate the performance of these two TIADC systems and the accuracy of the parallel multichannel-filtering approach, the effective and detailed test is done and introduced in chapter7. For the14Bit1600Msps high-speed high-resolution TIADC system, we give the test results of software based correction and hardware real-time correction respectively. The results indicated that the hardware real-time correction working well. For the8Bit10Gsps ultra-high-speed TIADC system, we present the software based correction results, which indicate that the performance of the TIADC system in the whole analog bandwidth is nearly the same as the typical performance of a single ADC chips given by the data sheet.At last, in chapter8, we give a summary of the work and the outlook for the next work in future. |
