Time-interleaved Based Super-high Speed Analog-to-digital Converter Research

Analog-to-Digital Converter (ADC) is the interface between analog world anddigital world, it functions as converting analog signal in nature to digital signal, takingthe advantage of digital signal processing (DSP), such as high reliability, high precisionand high stability. With the development of computer and DSP, ADC plays animportant role in modern radar, electronic warfare equipment and commication systemwhere system requires more and more from the performance of ADC because theenhancement of DSP ability.Undoubtfully, the process rate of ADC has become the keyrestrict of system performance. In many applications, the process rate of ADC has beenrequired more than GHz, so developing super-high speed ADC becomes a hot trend ofADC design.This thesis focuses on these trends, taking Time-Interleaved (TI) sampling ADC asthe study object. Basing on the penetrating into modern theory and technique ofsuper-high speed TI ADC, we designed a TI ADC product and discussed the key relatedtechnique, mainly including:First, this thesis analyzes the theory and popular realizing technique of modern TIADC, expanding from the following aspects: time-interleaved sampling architecture,low jitter multi-phase clock, analyszing mismatch between channels and the correctingthese mismatches, aiming to get a whole understanding of TI ADC for the next designstep.Then, based on the aboving theory analysis, a2-channels8-bit2GSample/s TIADC with the main credible technique is designed. Among these mainstreamtechniques, we emphasize on the whole sheme design, including:2-channel TI samplingarchitecture design, high precise low jitter clock circuit design, high speed interfacecircuit design and the digital calibration circuit design and serial programmableinterface (SPI) of channel mismatches.The Sub_ADC is designed with floding andinterpolating architecture according to the feature of super-high speed ADC. Besides,considering the actual application of the product, reliability design and high speedpackaging design are taken into account. Finally, the designed2-channel TI ADC is produced with0.35μm BiCMOSprocess. The testment results of the product are: Sample rate2GSPS, SNR≥43dB,ENOB≥6.9, DNL≤±0.5LSB, INL≤±0.8LSB, SFDR≥50dB, P≤1.8W. Thesespecifications are perfectly consonant with the previous defined ones when this thesisstarts which achieves the aim of research and design.