Design Of High-Speed Folding Interpolation ADC Sampling Time Mismatch Error Calibration Circuit

Compared to Full-Parallel Structure ADC, Folded Interpolated ADC can obtain high speed, reduce the chip area and power consumption at the same time. This structure has been widely used in high-speed ADC . But now the single-chip ADC can difficultly achieve the requirement of high sampling rate, So time interleaved structure ADC is being used more and more. However, there are various errors between the ADs, which will greatly affect the performance of the ADC. among them the sampling timing error between the channels is the most critical and most difficult to calibrate, and it become the focus of research in this field.In this thesis, we first did detailed research for the current situation of mismatch error calibration technology in time interleaved ADC channel, For 8-bit,single-channel sampling frequency of 500MHz, four-channel folding interpolation time interleaved ADC, analyzed the influence of the error between sub. channels on ADC outputs; and the necessity of designing the sampling time mismatch error calibration circuit is proved by theoretical analysis and behavior level modeling,It is concluded that the sampling timing deviation between the channels of the interleaved ADC should be less than 2.5 ps. Study the typical sampling time mismatch error calibration technique and determine to use fully differential analog calibration loop,the circuit converts the sampling timing deviation into duty cycle information ,it include edge detection circuit, fully differential continuous time integrator,transconductance amplifier and so on.The edge detection circuit converts the sampling timing deviation into duty cycle information, and we introduced a manual adjustment module in the circuit, slightly adjust the detected duty cycle information by changing the current flowing in the circuit,it can calibrate in the background. In the design of integrator we detaily described the choice and architecture of the op amp,and how to determine the RC constant of the integrator according to gain, swing, etc.In the transconductance amplifier, the linearity of the circuit is improved by negative feedback, and a very linear transconductance gain had achieved. At last, the calibration effect of the whole calibration loop is verified.In this thesis,we based on TSMC 0.18?m CMOS process,at 2V supply voltage,we use Cadence Spectre software to simulate the calibration circuit which we designed. The simulation results show that, for 1GHz differential input clock signal,while the sampling clock of four-channel is it's two divided- frequency which different in phases, when delay one of them 100ps, The calibration loop automatically calibrates the sampling time interval of the output signal to 500.308ps, When the manual control word is further changed, the sampling time interval is calibrated to 499.992ps, this reached a very high accuracy.