Design And Implementation Of Multi-channel High Speed Data Transmission System

In recent years, information collection and storage technology has been used extensively in military and civil fields. And with the progress of technology and the development of the times, these areas of acquisition and storage system are required higher and higher, and make the information collection especially high-speed data acquisition technology is the field of electronic information technology in the focus of the study. In high speed data acquisition system requires not only high speed analog to digital converter to realize data acquisition and reliable system to achieve the data transmission, storage and processing.The design and implementation of multi-channel high speed data forwarding system is a part of the high speed data acquisition and storage system. In this thesis, the forwarding system with high speed signal acquisition as the background, with Xilinx company Virtex-6 series FPGA as the main control chip, the Micron company capacity DDR3 SDRAM 2GB as the storage device. Forwarding system to receive the ADC data which bandwidth up to 32 Gbps, forwarding system with PCIE bus technology, can be implemented on computer 2GB or more amount of data storage.In this thesis, we first analyze the current situation of high speed data acquisition technology, and the corresponding high-speed data storage scheme. Then, according to the project technical indicators, this paper designs the overall hardware scheme and the overall logical scheme. At the same time, the chip selection of the equipment involved is also carried out. Then, the SDRAM DDR3 of the storage device in the forwarding system is introduced, and the structure of the SDRAM DDR3 controller is analyzed, and the user interface signal of the controller is described in detail. Immediately after that, in the FPGA to realize the four-channel high speed data transmission system, which include the use of DDR3 SDRAM and asynchronous FIFO completed the real-time data correct caching, and enhance the storage capacity of the low-speed sampling data. At the same time, cross clock domain signal possible metastable been processed. Finally, to achieve the forwarding system board level debugging, in this thesis, the design of the transmission system into a high-speed sampling projects, the normal work of the system and achieve the index system. It is proved that the forwarding the correctness of the system design.The characteristics of this thesis are as follows: on the one hand, the sampling rate of 4Gsps, the resolution of the 8bit sampling data of the correct cache, cache capacity of 2GB, and with the PCIE module, completed the sampling data into the computer’s target. On the other hand, through a number of asynchronous FIFO and SDRAM DDR3 memory, increased the storage capacity of the low-speed sampling data.