Multi-channel Ultra-high-speed Data Acquisition And Recording System Design And Realization

With the development of modern radar and telemetry technology, People want to gain more messages in time, to meet the demands of the growing complexities of signal processing. As the forehead of system, high speed data acquisition is demanded to put a lot attention to data acquisition rate and storage capacity.This paper makes use of the advantage of FPGA, including abundant internal resources, flexibility for designing and reconfiguration, and so on, combining with high speed AD, gigabit SERDES,and large capacity DDR2 storage chip, to compose a system for collection and storage for high speed data. The main work in this paper is as follows,First, according to given acquisition for performance, the overall design proposal for the system is constructed. Firstly, high speed AD chip is chosen for data collection, and that gigabit SERDES is used for serial-parallel conversion. Then large capacity DDR2 SDRAM is applied as buffer memory for the data and finally the data is sent with the use of the gigabit Ethernet high speed transmission technology. The system implementation block diagram is drawn based on the system scheme.The chips needed for various modules are chosen and hardware design is completed.Second, on the Xilinx XC5VLX50T chip, with the design principle of top-down and module division, the whole control section of the system is divided to several modules as clock signal generation module, DDR2 controlling module, high speed serial-parallel reception module based on Rocket 10, interface module and data transmission module based on Ethernet MAC.Each module is designed by the hardware description language Verilog HDL.Third, each module is simulated by the Modelsim and implemented by the XST synthesized tool. The result has proved that this system can satisfy the requirement.