The Designed Of Four-channel High-speed Data Reception And Storage System

Restricted by devices and process, a single ADC chip is very difficult to guarantee high sampling rate while maintaining high resolution. In order to increase the system sampling rate, data acquisition system usually adopt the way of time-interleaved sampling multiple low-speed parallel ADC chip to realize high speed data acquisition. With the increases of a single ADC chip performance, time-interleaved sampling multi-channel high speed data acquisition met new problems in the process of receiving and storing.In this paper, in view of four channel 10 bit, 1.25 GSPS ADC of time-interleaved sampling ADC as the goal, based on FPGA high-speed data reception and storage logic design, this system has realized the reception of four-channel 10 bit, 1.25 GHz high speed data flow accurately, and a large mount of data can be stored in the DDR3 SDRAM high efficiently and in real-time, Finally using PCI9054 as switching chip of PCI bus, to realize the high speed data upload. In this paper, the core of the research content includes the following three aspects:1. The constructed a logical structure of four-channel high-speed data reception and storage system. Aimed at the receiving, storage, and upload of four channel 10 bit, 1.25 GHz high-speed data stream, to build a logic structure is composed of data receiving module, data storage module, data upload module and SPI configuration module. Through close coordination between four modules, we can realize the stable transmission of a large amount of high speed data stream from the ADC to upper computer.2. In the design of a delay adaptive adjustment algorithm of IDELAY.Since path transmission delay of four channel 1.25 GHz data and the clock are difficult,it may lead to receive data in disorder. Using IDELAY delay adjustment mechanism of FPGA interface, designed a delay adaptive adjustment algorithm in this paper, in which a calibration algorithm through sampling clock to capture the center of the data window, to achieve channel 10 bit data alignment; Word calibration algorithm corrects the deviation between four-channel, to realize four-channel 40 bit data correctly received.3. we design a oriented DDR3 SDRAM virtual FIFO(VFIFO) logical structure. To decrease logic synthesis difficulty,external four-channel 1.25 GHz high-speed data within the FPGA is by frequency reduction to data flow of 160- bit, 312.5MHz. The number of RAM in the FPGA chip is limited,it’s unable to provide large data cache, and the data bandwidth of RAM is limited. Aim at the problem of data unenough space and low efficiency of storage,it designed a virtual logic structure of FIFO in the paper, through the way of read-write FIFO time-sharing multiplexing, joint DDR3 controller to realize the efficient storage.Proved by the FPGA test board, IDELAY delay adaptive calibration algorithm functions is correct, DDR3 SDRAM read-write efficiency is more than 85% in average, PC software can carry on the full display to the collected signals, the system logic function is correct. In this paper, we study the contents of high speed data reception, storage, and upload has very important significance...