Design Of Analog-to-Digital Converter Based-on Pipelined Architecture Applied To Touch Controller Chip

As a new kind of interactive interface，the touch screen has been gradually widely used inthe phone, tablet PC, the educational system, public information inquiries and other fields inrecent years. The touch control technology stimulates intergrated circuit developing to higherperformance, and has specific requirements for the ADC in touch control IC. In order to meetthe requirements of touch testing precise，the touch screen need for a high sampling precisionADC, which should be able to cope with the noise in highly integrated terminal equipments.And the ADC should also meet the low power requirements to adapt to battery-poweredapplications. For the key indicators such as speed, precision, power and circuit area，pipelinedADC is undoubtedly the most suitable structure for the compromise of these aspects.This paper studied and designed a pipelined ADC with11-bit precision and500Ksampling frequency which used in touch-screen control IC: Studied the main indicators of theADC and several typical structures, and determine the applicable pipelined architecture bycomparing the advantages and disadvantages and applications of the typical structure of ADC.A detailed analysis and design for the circuit structures of each typical unit of this pipelinedADC is given, including: CMOS sampling switch circuits, sub-ADC and sub-DAC circuits,the multiplying digital-to-analog converter (MDAC) circuit, and error correction circuit.Used bottom plate sampling and gate voltage bootstrapped switch for S/H circuit to improvethe sampling accuracy; used the Scaling Down technology to optimize the selection ofsampling capacitances of each stage; analysed and designed the error correction circuit for1.5bit/Stage ADC to improve the conversion accuracy without increasing circuit complexity.Based on GSMC0.18um3.3V CMOS process, each unit circuit and the whole circuit aresimulated. The results show that, when given an input of1.8Vpp and3.9KHz, the SFDR,SNDR and the ENOB achieve78dB,67dB and10.8separately with a500KHz samplingclock. The indicators meet the design requirements.