| Phase noise illustrates the stability and reliability of the short-term signal frequency, it is an important indicator in Electronic measurement field. Phase noise measurement plays an significant role in signal analysis and testing.This paper aims to complete the design and implementation of data channel in phase noise measurement system. To provide the underlying datalink support for the phase noise measurement system, the paper through the analysis of the overall structure of the phase noise measurement system to description the composition of data channel.The data channel send the front end of the analog signal acquired to digital circuits by analog-to-digital conversion circuit. The FPGA circuits use FIFO to realize data cache of entering digital signal.The digital signal is sent to DDR3 SDRAM memory by bit width conversion. When the data in the memory reaches a preset value, the FPGA circuit will control the ADC sampling and the data will be sent to DSP signal processing system using the high speed serial interface.This paper has completed the following Work:1. Analysing the overall structure and the function of each part in phase noise measurement system based on phase discrimination method and explaining the composition of digital signal datalink.2. Introducing the configuration and operation principle of the dual channel ADC and the design of FIFO interface. On this basis, the paper uses FPGA FIFO core generation to realize the functional simulation of different clock bits width conversion between the ADC and FPGA circuits.3. Introducing the development and the operating principle of the DDR3 SDRAM memory. Illustrating the Sequential operating principle of the DDR3 SDRAM memory and controller command.Using Xilinx Memory Interface Generation to generate memory controller and simulate its function. The read and write functions of the controller are validated on the FPGA hardware development board.4. Introducing the system composition of high speed serial interface, on this basis, the paper illustrates the internal structure of Xilinx Virtex-6 FPGA GTX transceiver. Using Xilinx FPGA core generation to generate GTX transceiver and stimulate the GTX transceiver interface function. |
