Design And Simulation Of DDR3 SDRAM Controller And PHY

With the development of semiconductor technology in modern times,the performance of processors and memory in computer systems has improved significantly and work frequency also increased rapidly.But the difference of manufacturers between processor and the memory leads to the different development pace of the two.The performance of the processor far exceeds the memory."Storage wall" problem becomes very serious.Memory access efficiency,bandwidth,operating frequency is difficult to meet the needs of modern processors and the ability of the processor is difficult to show up,so the overall performance of the computer system is also limited.The memory controller acts as a bridge between data transfer between the processor and the memory,so it is important to study an efficient memory controller.According to the DDR3 SDRAM standard,the paper analyzes the various timing parameters of DDR3 operation,explains the concept of Page Hit,Page Direct Hit and Page Miss and points out the factors that affect DDR3 reading and writing efficiency which is addressing conflicts.And then it proposes that adjusting the order of execution of reading and writing commands and to execute different commands belong to different Bank in cross-way to improve the work efficiency.PHY will be connected to the controller and memory,and the DQS hardcore in PHY output DQS signal and adjust the DQS signal delay to complete the write leveling.The DQS signal is detected using the DQS hard core and the sampled DQS signal is shifted by 90 degrees as the sampling clock of the DQ signal,then the read calibration is done.In this paper,the Verilog HDL language is used for the design and simulation of the modules.