Design And Verification Of SDRAM Controller Applied To PLB4 Architecture

In recent years, with the rapid development of information society, technology makes progress with each passing day in the field of communication, computer, etc.In these fields,the the application of memory is becoming more and more important.Because the effect of memory on the chip’s performance plays a vital role,design a high-performance, reliable and good memory is necessary.SDRAM is a high speed dynamic random access memory with the advantages of high capacity, high speed, high integration density,low price and low power consumption.The memory is widely used in graphics acceleration and all kinds of SOC system,which make it become to the most important storage medium.The synchronous interface and pipeline architecture make it has a very large data transmission speed.Now,the clock frequency of SDRAM has reached to 100 MHz.Because the SDRAM controller has been a weaknesses of data caching system,the designation of SDRAM controller is very important.Through the research of SDRAM agreement,this paper make a focus on the design of SDRAM controller,such as cross clock domain and the analysis of read/write timing,finaly design a SDRAM controller applied to the PLB4 Bus. This SDRAM controller has the advantages of easy-control and good-practical.This paper introduces the PLB4 bus structure firstly,then introduces the typical application of SDRAMMCPLB4 structure.According to its composition, each module are explained respectively,about the methods and ideas of the design.the Plb_slaver module is the interface of SDRAM controller and PLB bus,and conform to the standard of PLB4.6 interface specification.The Plb_slave support 128 bit master,1-16 byte single operation,4 word and 8 word line operation,double word and 4 word burst operation.It also support pipeline operation, and provide the depth of six PLB request queue, integrate 256 bytes read buffer and 512 bytes write buffer internally.The MCIF2 SD module is a conversion interface, to match the data rate, map timing and convert function.The SDRAM controller module contain 7 sub-mudule: mem_reg,memctrl_busarb,sdram_addrctrl,sdram_astoref,sdram_datactrl,sdram_fsmctrl and sdram_pagectrl. According to its composition, each module are explained respectively.At last, instantiate SDRAMMCPLB4 to the IBM Toolkit and use BFL language to write testing code. Under the LINUX operating system,convert the BFL file to the.v file. Write a script under NCsim environment and Run the simulation. Verification results show that the SDRAM controller meet the requirements of transmitting data between PLB bus and SDRAM controller.