The Study Of Algorithm For Successive Approximation Analog To Digital Converter

As successive approximation analog to digital converter (ADC) features medium speed and high accuracy, it is suitable to realize ADC between 12 bits and 16 bits. It is popularly used in battery powered instruments, industrial control and data collection applications. In this paper, algorithms that are suitable for a 16 bits successive approximation ADC were studied and designed on its features. Finally, the designed chip was taped out and tested.When realizing high accuracy successive approximation ADC, the traditional binary searching algorithm is too simple to satisfy 16 bit ADC design requirement. In this paper, the traditional algorithm was optimized and it had been proved that the optimized algorithm had the same function as the traditional one while it cut down the die size a lot. When considering the parasitic capacitors and process variation, the coupling capacitor calibration algorithm and the binary weighted capacitor mismatching calibration algorithm were also proposed to improve the accuracy of the ADC.In the high accuracy ADC design, the combination of the algorithm and the real circuit design is a key. On the basis of the whole circuit design, the error calibration circuit and its error storing and accumulation circuit were added to the traditional charge redistribution DAC to realize the binary weighted capacitor array mismatch calibration algorithm. The coupling capacitor error calibration algorithm was mainly for the parasitic capacitor in the three key joints in the DAC. So this algorithm was realized by the optimization of layout after the extraction of the parasitic capacitors.