A 12-bit 100MS/s Pipelined A/D Converter

The pipelined analog-to-digital converter is widely used in high-speed, high-resolution analog-to-digital conversion applications. The advantages of using the pipelined architecture include low power and small area. One drawback of the pipelined architecture is that when used for high-resolution applications, the first few stages of the pipelined require high linearity and low noise. With scaling of CMOS technologies, high-precision analog building blocks become more difficult to design, while the cost of digital circuits shrinks in term of both area and power. One approach to designing a pipelined ADC in modern CMOS technologies is to shift design complexity from the analog domain to the digital domain. In particular, a pipelined analog-to-digital converter can be designed with low-precision analog building blocks and the resulting non-idealities can be corrected digitally.This article is based on SMIC 0.13μm Standard CMOS 1P6M process, design a 12-bit 100MS/s pipelined analog-to-digital converter.(1) at 1.2V, a high gain, wide bandwidth of two fold cascade operational amplifier was designed in this paper, resolved the gain error and the circuit nonlinearity establish error.(2) a high-speed dynamic comparator was designed by us to reduce kick-back noise while increasing the speed almost no static power was designed in this paper.(3) a flip-around of sample-and-hold circuit was designed in this paper. In order to improve the linearity of the overall circuit, design a bootstrapped switch.(4) We design the stage of pipelined analog-to-digital converter using 1.5bit/stage with 0.5bit redundancy bits to improve the performance of pipelined ADC.(5) a digital calibration circuit was design in this paper, after calibration, greatly enhance the accuracy and linearity of pipelined ADC.