Design Of Key Modules Of 12Bit 40MSPs Pipeline ADC

Analog signals are produced in nature, with the rapid development of information technology and VLSI, in order to play the advantages of digital signals processing, many systems firstly turn analog signals into digital signals for processing, then turn digital signals into analog signals, so the design and performance of data converter is very critical.At present, such as SONET, DVC, Base Station, DVD Audio and other electronic equipments, they require ADCs with speed from 100 KHz to 75 GHz and resolution from 6 bits to 24 bits. And the equipments we use often almost require ADCs with speed of several hundred MHz and resolution from 10 bits to 18 bits. The main architecture that can meet these requirements simultaneously is pipelined ADC.There are several non-idealities in pipelined ADC, such as the finite gain and finite bandwidth of amplifiers, the input offset of comparator, the on-resistance of sampling switches, the mismatch of capacitors. Therefore, we have to consider these questions carefully when designing the ADC. In the design of this subject, we analyzed these non- idealities sufficiently and made the performance of the pipelined ADC to meet the design targets through adjusting architecture and parameter of the ADC circuits. Finally, we choose 1.5 bit/stage of pipelined ADC by considering the trade-off between power and speed. The whole ADC includes 10 1.5bit/stage and a 2 bit FLASH stage with digital error correction circuit.The key modules of a 12-bit 40 MS/s pipelined ADC is designed in this paper, which is fabricated with SMIC 0.18 CMOS process. After the previous simulation for circuits and PS simulation for layout with parasites extraction, when the input signal is a sinusoid signal and the sampling frequency is 40 MHz, the ADC achieves SNR of 70.1 d B, SFDR of 74.9 d B and the ENOB of 11.35 bits, which reach the initial design targets of 40 MHz sampling frequency and ENOB of 11 bits.