The Design And Implementation Of Gigabit Ethernet MAC Controller In X-DSP

Ethernet is the most important computer network communication technology. After 40 years’ development, Ethernet technology has been widely used in industrial control and communication systems. The MAC Controller is an important equipment for Ethernet., and implements the function of MAC sublayer, which is in the data link layer of ISO module. Based on the background of the digital signal processor X-DSP, the design of a Gigabit Ethernet MAC controller is descript in this paper. The X-DSP is developed independently in our school, with multi-core and high performance. The MAC controller provides a network interface of gigabit transmission rates for the X-DSP.With the study of the performance requirement of X-DSP and the deeply function analysis of the Ethernet MAC sublayer, the architecture of the MAC controller and the clock management plan are devised. Independent data and configuration paths are designed for communication between the MAC controller and the interconnect bus in the DSP. The transmission in the data interface is according to the AXI protocol, which is based on the burst and supports the parallel read and write transaction. The design of the AXI data interface ensures the efficient transmission of receiving and sending data. While the configuration interface uses the simplified AXI protocol to manage the registers.To achieve the transmission rates of 10Mbps/100Mbps/1000 Mbps, two types of the PHY interface, MII and GMII, are designed in this thesis. The MAC controller provides a variety of filters, such as address matching and Hash table seeking; and uses the parallel CRC-32 algorithm for the checksum of the Ethernet frames. Meanwhile, the MAC controller has two communication modes: half-duplex and full-duplex. In the half-duplex mode, the transmission is based on the CSMA/CD protocol and the back-off mechanism. While in the full-duplex mode, the solution of flow control is programmed on the pause frame.Two asynchronous FIFO, with the depth of 512 and 133-bit,are designed to buffer the transmitting and receiving data, as well as some control signals. At the sime time, the asynchronous FIFOs deal with the problem of synchronization between the signals, which are in the different clock domains.Finally, according to the down-up method, module level and system level platform are built to simulate the function and timing of the MAC controller. In conclusion, the MAC controller designed in this paper achieves the goal.