Two Asynchronous Fifo Design And Comparative Study

FIFO (First-in First-out) is a storage device widely used in digital system. It can store a continuous stream of data and output it with the same order. Input and output can use different rates. Therefore, they are often used in VLSI systems, by smoothing the fluctuation of the production rate of data to achieve maximum efficiency in transmission channel. As an independent chip, it has a wide range of applications in telecommunications, image processing, mass storage systems, digital signal processing and so on.This article at first introduced the development status and classification of FIFO. It is divided into two basic types based on the data flow patterns. Then some of the key issues in the asynchronous FIFO design were discussed. Next two different types of asynchronous FIFO design were given: the SRAM based asynchronous FIFO controlled by counters and the asynchronous FIFO using token rings and common data bus. The former used full custom design flow and the latter used a semi-custom design process. Finally, after we got circuit and layout of the two FIFOs, the parameters of these two FIFOs were compared.In the comparison, we found that, when the depth was less than 192, the token-based asynchronous FIFO had certain advantages in time delay over the SRAM-based asynchronous FIFO, the smaller the depth, the greater the advantage. When the depth was larger than 192, the SRAM-based asynchronous FIFO gradually reveal the advantages comparing to the token-based asynchronous FIFO, because it increase in delay more quickly. When depth was less than 473, the token-based asynchronous FIFO had certain advantages in power consumption. The fully customized asynchronous SRAM-based FIFO's advantage on the area compared to the semi-custom token-based FIFO is more apparent no matter how much the depth is.This design of asynchronous SRAM-based FIFO is the research projects of our Lab with the design depth of 4K, the access time 12ns, peak power less than 1W, the working frequency 50Mhz. The 0.5um CMOS technology is used,the fabrication process is carried out successfully. After testing , we get that the Access Time of the chip is 10ns,the circuit can work stably in the 50Mhz frequency with the peak power less than 800mW, fully meet the project requirements. Token-based asynchronous FIFO using 0.35um COMS library to complete layout design and simulation, the depth is 64. After post-simulation, the Access Time is 0.94ns (The impact of the PADs is not included).