Design And Implementation Of High-throughput Data Interface Between MAC And Baseband Based On FPGA

With the evolution of mobile communication from 3G to LTE or LTE-Advanced,the base station is upgrading constantly,including not only support multi-carrier in a single wireless mode but also support multi-mode in a single transmitter path,which means evoluting to Multi-Standard Radio Base Station(MSR BS).For example,multi-carrier in multi-mode of GSM,TD-SCDMA and LTE can be transmitted simultaneously in a multi-standard radio base station.Obviously,multi-standard radio base station needs to have the ability to process and transmit high-throughput data.This thesis researches the design and implementation of the high-throughput data interface between the MAC protocol processing board and the baseband processing board based on FPGA,which aims to provide solution for the realization of high-throughput interface for the Multi-Standard Radio Base Station.The whole design architecture is:MAC protocol processing board is connected with PCI Express interface,PCI Express interface is converted to 10-Gigabit Ethernet interface in FPGA,and the baseband processing board is connected with 10-Gigabit Ethernet interface,and the theoretical data throughput of the whole link can be 8Gbps.Firstly,this thesis researchs PCI Express bus protocol standard and analyzes the performance differences between DMA and no DMA transmission.Then concludes that DMA transmission can obtain better performance than no DMA.Then complete the internal logic of PCI Express interface based on DMA transmission.Finally,complete the verification to the logic design through the board level testing.Secondly,this thesis analyzes the improvement of the 10-Gigabit Ethernet MAC layer and physical layer protocols compared with the Gigabit Ethernet.Then complete the 10-Gigabit Ethernet MAC and physical layer protocol in IEEE802.3ae standard based on Virtex-5 FPGA and the physical layer chip.Then complete the internal logic of 10-Gigabit Ethernet interface in FPGA and the verification to the logic design through the board level testing.Finally,this thesis analyzes the metastable state problem may be triggered in clk domain crossing based on FPGA design.Then elaborates three methods to solve the clock domain crossing problem:double latch method,special handshake method and the memory synchronization method.After comparing the three methods,choose the asynchronous FIFO to connecte the PCI Express interface and the 10-Gigabit Ethernet interface to solve the problem of clk domain crossing.In a word,this thesis completes the design and implementation of high throughput data interface between the MAC protocol processing board and the baseband processing board through the research and analysis,the logic implementation and the board level testing.It provides the technical support to the multi-standard radio base station and provides a high throughput data transmission path for mobile communications system evolution from 2G/3G to 3.9G/4G.