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The Design Of Asynchronous FIFO Memory

Posted on:2008-02-13Degree:MasterType:Thesis
Country:ChinaCandidate:J SuFull Text:PDF
GTID:2178360215951004Subject:Microelectronics and Solid State Electronics
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FIFO is a method of first in and first out. Asynchronous FIFO is a general way to communicate between different clock domains. This thesis makes an analysis and research for asynchronous FIFO memory and presents two schemes of designing this circuit.The design of asynchronous FIFO meets with two troubles, metastability and how to generate empty and full flag correctly. Address are synchronized into the opposite clock domain before generating synchronous FIFO full or empty status signals. Because the FIFO is either empty or full when the pointers are equal, therefore, something else has to distinguish between full and empty. Two methods are proposed to overcome these problems. One method is to add an extra bit to each pointer. Another solution, divides the address space into some quadrants. Because read pointer and write pointer are from different clock domains, synchronizing them to another clock domain may cause the output to go metastable. For this problem, there are two solutions described in this paper. One common technique is to use Gray code pointers and only one bit may go metastable. Another solution is that the binary pointers are sampled and handshaking control signals are used. An optimized gray code circuit is proposed to improve FIFO memory frequency. In order to cut down the quantity of synchronous registers and decrease area, this paper discusses the FIFO memory design style with asynchronous pointer comparison and asynchronous full and empty generation.The Verilog RTL code for two FIFO memory styles is listed in this paper. The results of ModelSim simulation and FPGA verification both indicate the asynchronous FIFO design is feasible.
Keywords/Search Tags:FIFO, metastability, asynchronous clock domains, synchronize, Gray code
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