The Design Of An Asynchronous FIFO For The PCI Interface Controller

PCI is a bus which connect CPU and other peripherals. An asynchronous FIFO was designed in this paper and it is one portion of the PCI interface controller. Asynchronous FIFO is one of major portion of the PCI Interface Controller, and asynchronous FIFO is a general way to communicate between different clock domains. When the asynchronous FIFO was designed, two troubles were meeted. There is metastability and how to generate empty and full flag correctly. For these problems, synchronizer and Gray code were used as the pointers of asynchronous FIFO to avoid metastability. Two different projects were used to assert full flag and empty flag. An extra bit was added for the each pointer in the first project. When the increment of write pointer/read pointer reach the final FIFO address, the FIFO wrap and toggle the extra bit. By compared the extra bit, it can be distinguished whether the read pointer catch up the write pointer, or the write pointer catch up the read pointer. The characteristic of Gray code was used in the second project. Two MSBs of Gray code divides the address space into four quadrants. If the write pointer is one quadrant behind the read pointer, this indicates a "going full" situation. If the write pointer is one quadrant ahead of the read pointer, this indicates a "going empty" situation. The process of ASIC was used in this design. By using verilog HDL, the RTL implement of two projects were achieved. By using simulation of RTL, the logic function of two projects were validated. By using synthesis, the gate-level circuit of two projects were accomplished. By using STA, the timing of two projects were validated. With the result of simulation, synthesis and STA, the two projects were analyzed from the structure of circuit, frequency, area and power. Then the second project was choosed for placement and routing. By using auto placement and routing, the floorplan, clock tree synthesis, placement and routing were achieved. Finally, the asynchronous FIFO of the PCI interface controller was accomplished.