Gigabit Ethernet Mac Controller Ip Core Design

The design of Gigabit Ethernet MAC controller soft IP core is descript in the dissertation. The main content of this dissertation is the design of 10M/100M/1000M Ethernet MAC controller and AHB bus slave interface. Finally this dissertation implements a Gigabit Ethernet MAC controller IP core which is AHB bus compatible. The IP core is tested by simulation tools as well as verified by FPGA.After determining the system architecture , following the TOP_DOWN design methodology , interface signals between modules and the interactive approach is designed in detail firstly , and then the micro architecture of controller and data path within each module is designed and implemented using Verilog HDL. Arithmetic and protocols to be implemented in these modules , such as CSMA/CD, CRC, HASH,and AHB, is introduced and implemented by hardware In this dissertation. A simplified AHB slave interface is designed, which supports single operation and fixed length burst operation. A synthesizable coding style is used, and resource costs, performance and robusticity is considered as well, which promises a stable, smart and low cost MAC controller IP core. Last, testbench and FPGA prototype system is built, and the MAC controller IP core is firstly simulated using Modesim, then synthesized using Quartus II 8.0 tool, and at last downloaded to FPGA development board to run real-time simulation.The innovation point of this thesis is bringing forward a new kind of multiple mode asynchronous FIFO whose read pointer can be loaded by other module, and use it for buffer architecture design, which can realize successive strorage of frames in MAC controller buffer, and can easily realize frame retransmittion and bad frame drop function as well. This is an improment of the exsiting MAC controller who has low efficiency or poor facility in buffer management.