Simulation And Research Of Set In SOI CMOS Technology

Compared with the traditional bulk silicon process,SOI(Silicon On Insulator) technology for its high reliability,low power consumption,strong anti-radiation, gradually become the mainstream anti-radiation integrated circuit manufacturing process.With shrinking process geometries, radiation sensitivity of integrated circuits is also increasing, soft errors caused by SEE(Single Event Effect)will become a major threat to integrated systems. In this paper, the numerical simulation method is used to study the performance of MOSFET anti-SET(Single Event Transient) based on SOI technology.The article includes the following:Based on the analysis of existing SOI device simulation environment establish an integrated device simulation platform. And on this basis,create 3D model of the body-contact with the partially depleted SOI devices.In this paper,SOI NMOSFET based on the 40 nm process size were calibrated.Proposing the concept of dynamic effect factor and calibration method of qualitative and quantitative analysis,improving the accuracy of the process calibration and shorten the calibration cycle.In this pape,the SET generation of bulk silicon and SOI process was simulated by using the hybrid methods.Combining with the simulation results analyzed the SET pulse generation mechanism.At the same time, analyzed the common converge problems and proposed solutions.about this problem combining with the examples of simulation.In this paper, SOI PMOSFET key structural parameters and temperature were simulated, analyzed the impact on SET pulse width. The relationship between the key parameters and SET pulse was shown through the graph. SET sensitive area of the device is an important indicator to measure its anti-radiation properties. In this paper, the 90 nm process PMOSFET was studied. Simulated the SET sensitive area of bulk silicon and SOI process devices respectively.Compared and analyzed the simulation results about bulk silicon and SOI process devices.