Research On Pulse Quenching And Charge Sharing Effect Induced By Single Event On Sensitive Area Of Integrate Circuits

The rapid development of China’s manned space flight science and technology since 21 st century brings out a higher request on the work of anti-radiation technology for advanced integrated circuits(ICs). With the ICs technology scaling, the radiation-induced soft errors are becoming a great concern to circuit reliability. And the contribution of single event transient(SET) to the whole soft errors is increasing as the technology scales. Especially, charge sharing may lead to the multi-node charge collection has made the SET analysis more and more complex.For nano technology, sensitive area resulted in Single-Event Effect has able to cover more than one device. On the one hand, charge sharing effect makes radiation-harden ICs facing failure. On the other hand, charge sharing effect may lead to the propagating SET pulsewidths and cross section area reducing through Pulse Quenching, and then lead to the sensitive area of ICs reducing, thus it is meaningful to studies the relationship between Pulse Quenching effect and sensitive area of ICs for irradiation ICs design. Based on nano CMOS technology, this paper investigated the impact of Pulse Quenching effect on sensitive area of ICs, The main work and contributions of this thesis are as follows:(1) Under on 65 nm CMOS bulk silicon technology by 3D TCAD simulation, it is found that the Pulse Quenching effect can lead to the sensitive area of inverters reducing, the higher energy of the incident particle, the bigger impact of Pulse Quenching effect on sensitive area of inverters. We propose that Gate Isolation technology which should be used to enhance the Pulse Quenching effect between transistors, 3D TCAD simulation showed that the sensitive area of inverters reducing more.(2) Under on 65 nm CMOS bulk silicon technology by 3D TCAD simulation, it is found that the Pulse Quenching effect can lead to the sensitive area of SRAMs reducing, the higher energy of the incident particle, the bigger impact of Pulse Quenching effect on sensitive area of SRAMs. We propose that Gate Isolation technology which should be used to enhance the Pulse Quenching effect between transistors, 3D TCAD simulation showed that the sensitive area of SRAMs reducing more.(3)Under on 65 nm CMOS SOI technology by 3D TCAD simulation, it is found that the sensitive area of transistors is smaller than bulk silicon technology. Gate Isolation technology made the Pulse Quenching effect occur between transistors, lead to the sensitive area of inverters reducing, the higher energy of the incident particle, the bigger impact of Pulse Quenching effect on sensitive area of inverters.