Single The Particle Pulse Width Suppression And Single-particle Testing Method Study

With decreasing feature size, increasing complexity, lower operating voltage and higher clock frequency, single event effects (SEE) have become one of the most important issues that impair the reliability of deep submicron integrated circuits. This thesis will focus on the modeling, mechanism and testing of SEE.First of all, NMOS and PMOS are modeled as three dimensional devices in 130-nm and 90-nm bulk CMOS technology. The ion track is modeled as three dimensional model with time and space variation. We also propose a calibration method by combining process calibration with device editing.Next, we propose four pulse quenching mechanisms: NMOS-to-PMOS, PMOS-to-NMOS, NMOS-to-NMOS and PMOS-to-PMOS, then verifies them using 3-D TCAD simulations. The three major contributions are:1) Pulse quenching is more prominent for PMOS-to-NMOS, NMOS-to-NMOS and PMOS-to-PMOS cases in 90 nm process.2) Pulse quenching in general correlates weakly with ion LET, but strongly with incident angle and layout style (i.e. spacing between transistors and n-well contact area).Finally, we design and realize the SEE static characterization of FPGA, including single event latch-up, single event upset (including user flip-flops, configuration latches and block memory) and single event functional interrupt. We also propose and realize SEE dynamic characterization of FPGA, including accelerated test and JTAG-based fault injection test.