Researches On The Temperature Correlation Of Single-Event Transient Pulse Width Under Advanced Technology

In the space environment,aerospace application integrated circuits usually need to work in extremely low or high temperature environments.Temperature has an impact on the electrical parameters such as the carrier mobility of the device.The changes of electrical parameters and the appearance of new features will affect the charge collection of the device.The amount of charge collection will directly affect the single-event transient pulse sensitivity of the transistor.Therefore,temperature will affect the SET sensitivity of the transistor.As the technology codes scaling down below 28-nm,advanced technology such as Fully Depleted silicon-on-insulator(FDSOI)and FinField Effect Transistor(FinFET)are applied on the integrated circuit design.Compared with bulk process,FDSOI devices and FinFET devices have many differences in structure and technical parameters.Because both these structural parameters and temperature will all affect the charge collection of the transistor,the performance of SET temperature dependence in transistor will change.Therefore,under the advanced technology,studying the influence of temperature on the SET pulse width and considering the influence of structural parameters on the temperature dependence of the SET in the transistor has become a new problem that needs to be studied to accurately evaluate the characteristics of the single event effect of the advanced technology.This paper takes 28-nm bulk silicon process,22-nm FDSOI process and 16-nm FinFET process as the research objects.Using three-dimensional TCAD numerical simulation combined with theoretical analysis to study the effect of temperature on SET pulse width and influence of the structure parameters on temperature dependence of SET.The main work and results of this article mainly include the following parts:(1)Under the 28-nm bulk process,verifing international inferences about the influence of temperature on SET pulse width.Studies find that the electrical characteristics of the device have an anti-temperature effect.The worst case of SET still occurs at high temperatures rather than low temperatures.The influence of the process corner on the temperature dependence of the SET pulse width is also studied.It is found that under the SS corner,the SET pulse width is the largest but the temperature dependence is the lowest.While under the FF corner the SET pulse width is the smallest but the temperature dependence is the highest.The effect of the triple-well structure on the temperature dependence of the SET pulse width is also studied.The N+ deep well can significantly increase the SET pulse width in the NMOS transistor and enhance the temperature dependence of the SET pulse width of the device.The P+ deep well can significantly reduce the SET pulse width in the PMOS transistor and enhance the temperature dependence of the SET pulse width of the device.(2)Under the 22-nm FDSOI process,the SET pulse width of the device exhibits an anti-temperature effect at low voltage.The anti-temperature effect weakens with the increase of the supply voltage.When the supply voltage is above 0.6V,the SET pulse width shows very low temperature dependence.The influence of the process corner is also studied.Under low voltage,the anti-temperature effect of SET under the SS process corner is the most serious.Under high voltage,the SET pulse width under FF process corner has the greatest temperature dependence.It is proposed for the first time that the depth of the buried oxide layer plays an important role in the temperature dependence of the SET pulse width in the FDSOI technology.When the depth of the buried oxide layer is less than 30 nm,the influence of temperature on the saturation current of the device dominates,and the SET pulse width in the device exhibits an anti-temperature effect.When the depth of the buried oxygen layer exceeds 30 nm,the influence of temperature on the amount of charge collection begins to dominate,and the SET pulse width gradually increases with the rising of temperature.(3)Under the 16-nm bulk FinFET process,the simulation results show that the electrical characteristics of the 16-nm FinFET transistor have an anti-temperature effect,but the SET pulse width caused by heavy ion does not have an inverse temperature effect.The SET pulse width gradually increases with temperature.The influence of gate size and threshold voltage on the temperature dependence of SET pulse width is studied for the first time.At room temperature,devices with larger gate size and lower threshold voltage have better resistance to high LET heavy ion irradiation.Similarly,the larger the gate size of the device,the lower the threshold voltage,and the lower the temperature dependence of the SET pulse width.This paper focuses on the influence of temperature on the SET pulse width under advanced processes such as FDSOI technology and FinFET technology.The influence of structural parameters such as process corner,the depth of buried oxide and gate size on the temperature dependence of the SET pulse width is considered.The research content of this paper makes progress in the understanding of the SET characteristics in the device and citcuits under FDSOI of FinFET technology.Many original data have also been obtained.This paper provides a theoretical guidance for the design of radiation-resistant integrated circuits under advanced processes in the future.