The Design Of Two-Mode Matrix Transpose Memory In 40nm Process

Matrix transposition is greatly applied in the domain of scientific computation. Such as, discrete fourier transformation(DFT) and the sliding window algorithm that frequently applied in image, video need a large number of matrix transpose operation which determine the DSP’s efficiency of scientific caculation and graphics-video applications. It is quite essential to design matrix transpose memory with high transposition efficiency for DMA in military FT-XXX DSP chip that provides fixed and floating-point arithmetic calculations. Based on the design demand of FT-XXX chip, this paper proposes a design of two-mode matrix transpose memory in 40 nanometer CMOS technology. The main research work in this paper is as follows.Firstly, based on the design requirement of high performance, low power and small area, we choose the full-custom technique to finish the design of two-mode matrix transpose memory with 16-word×16-bit 1-read, 1-write port in 40 nm process. The post-layout simulation shows that the two-mode matrix transpose memory which output delay is 290 ps, dissipative power is 1.17 mW and the layout area is 33×30μm2 works well at 1GHz under the typical condition. These results meet the demand of the design.Secondly, based on the 16-bit design, we implement the schematic and physical design of 1024-bit two-mode matrix transpose memory. After the hierarchical circuit design, we introduce the verification method of two-mode matrix transpose memory. We use equivalence checking tool called Formality to verify its function accuracy. Then by manual placing and automatic routing, the measured absolute delay and layout area of 1024-bit two-mode matrix transpose memory are 0.293 ns and 512x120μm2 respectively which reached the design goal.Lastly, we design and implement the memory built-in self test(MBIST) of two-mode matrix transpose memory with high fault coverage. This paper thoroughly researched a general MBIST structure and test measurement. At the same time, we also exploit a new set of testbench correspondly and analyze the stuck-at-fault1/0 detecting method. After equivalent replacing the original two-mode matrix transpose circuit, we get 91.40% fault coverage.